Reorganized repository, added circuit schematics

This commit is contained in:
Jonathan Montineri
2019-02-15 15:27:00 -05:00
parent 655dc8c798
commit db7a4a47e8
21 changed files with 6500 additions and 0 deletions
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_01x04
#
DEF Connector_Generic_Conn_01x04 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Generic_Conn_01x04" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 50 -250 1 1 10 f
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X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
X Pin_4 4 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x08
#
DEF Connector_Generic_Conn_01x08 J 0 40 Y N 1 F N
F0 "J" 0 400 50 H V C CNN
F1 "Connector_Generic_Conn_01x08" 0 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
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X Pin_6 6 -200 -200 150 R 50 50 1 1 P
X Pin_7 7 -200 -300 150 R 50 50 1 1 P
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ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x11
#
DEF Connector_Generic_Conn_01x11 J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Connector_Generic_Conn_01x11" 0 -600 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
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S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
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ENDDEF
#
# Connector_Generic_Conn_01x12
#
DEF Connector_Generic_Conn_01x12 J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Connector_Generic_Conn_01x12" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
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S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
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S -50 550 50 -650 1 1 10 f
X Pin_1 1 -200 500 150 R 50 50 1 1 P
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X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 -200 0 150 R 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 -200 -200 150 R 50 50 1 1 P
X Pin_9 9 -200 -300 150 R 50 50 1 1 P
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ENDDEF
#
# Connector_TestPoint
#
DEF Connector_TestPoint TP 0 30 N N 1 F N
F0 "TP" 0 270 50 H V C CNN
F1 "Connector_TestPoint" 0 200 50 H V C CNN
F2 "" 200 0 50 H I C CNN
F3 "" 200 0 50 H I C CNN
$FPLIST
Pin*
Test*
$ENDFPLIST
DRAW
C 0 130 30 0 1 0 N
X 1 1 0 0 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library
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update=2/15/2019 9:12:44 AM
version=1
last_client=eeschema
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
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