Avoid "chunkiness" of UART FIFO availability #511

Merged
earlephilhower merged 3 commits from serblast into master 2022-03-16 18:46:20 +03:00
earlephilhower commented 2022-03-12 22:27:31 +03:00 (Migrated from github.com)

The UART FIFO will generate an IRQ to transfer data into the SerialUART
FIFOs either every 4 received bytes, or every 4 idle byte times. This
causes the ::available count to report "0" until either of those two
cases happen, causing a potentially delay in data becoming available to
the app.

Change the code to pull data from the HW FIFO on a read/available/peek.
Use a non-blocking mutex and IRQ disabling to safely empty the FIFO from
user space. The mutex added to the IRQ is non-blocking and will be
a single CAS the vast majority of the time, so it should not impact the
Serial performance.

Fixes #464 and others where setPollingMode() was needed as a workaround.

The UART FIFO will generate an IRQ to transfer data into the SerialUART FIFOs either every 4 received bytes, or every 4 idle byte times. This causes the ::available count to report "0" until either of those two cases happen, causing a potentially delay in data becoming available to the app. Change the code to pull data from the HW FIFO on a read/available/peek. Use a non-blocking mutex and IRQ disabling to safely empty the FIFO from user space. The mutex added to the IRQ is non-blocking and will be a single CAS the vast majority of the time, so it should not impact the Serial performance. Fixes #464 and others where `setPollingMode()` was needed as a workaround.
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