Update version

Fix JLink device names for RP2350 in PIO boards (#3001 )
Add BigTreeTech SKR-Pico (#2988 )
2025-06-19 18:36:46 -07:00 · 2025-06-19 18:30:37 -07:00 · 2025-06-19 12:36:20 -07:00 · 2025-06-19 11:55:06 -07:00 · 2025-06-19 11:16:53 -07:00 · 2025-06-16 12:29:12 -07:00
298 changed files with 11800 additions and 2345 deletions
@@ -10,7 +10,7 @@ jobs:

 # Consistent style, spelling
  astyle:
-    name: Spelling, Style, Boards, Package
+    name: Spelling, Style, Boards, Package, PIO
    runs-on: ubuntu-latest
    steps:
    - uses: actions/checkout@v4
@@ -19,13 +19,8 @@ jobs:
    - name: Run codespell
      uses: codespell-project/actions-codespell@v2
      with:
-        skip: ./ArduinoCore-API,./libraries/ESP8266SdFat,./libraries/Adafruit_TinyUSB_Arduino,./libraries/LittleFS/lib,./tools/pyserial,./pico-sdk,./.github,./docs/i2s.rst,./cores/rp2040/api,./libraries/FreeRTOS,./tools/libbearssl/bearssl,./include,./libraries/WiFi/examples/BearSSL_Server,./ota/uzlib,./libraries/http-parser/lib,./libraries/WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino,./libraries/HTTPUpdateServer/examples/SecureBearSSLUpdater/SecureBearSSLUpdater.ino,./.git,./libraries/FatFS/lib/fatfs,./libraries/FatFS/src/diskio.h,./libraries/FatFS/src/ff.cpp,./libraries/FatFS/src/ffconf.h,./libraries/FatFS/src/ffsystem.cpp,./libraries/FatFS/src/ff.h,./libraries/lwIP_WINC1500/src/driver,./libraries/lwIP_WINC1500/src/common,./libraries/lwIP_WINC1500/src/bus_wrapper,./libraries/lwIP_WINC1500/src/spi_flash
+        skip: ./ArduinoCore-API,./libraries/ESP8266SdFat,./libraries/Adafruit_TinyUSB_Arduino,./libraries/LittleFS/lib,./tools/pyserial,./pico-sdk,./.github,./docs/i2s.rst,./cores/rp2040/api,./libraries/FreeRTOS,./tools/libbearssl/bearssl,./include,./libraries/WiFi/examples/BearSSL_Server,./ota/uzlib,./libraries/http-parser/lib,./libraries/WebServer/examples/HelloServerBearSSL/HelloServerBearSSL.ino,./libraries/HTTPUpdateServer/examples/SecureBearSSLUpdater/SecureBearSSLUpdater.ino,./.git,./libraries/FatFS/lib/fatfs,./libraries/FatFS/src/diskio.h,./libraries/FatFS/src/ff.cpp,./libraries/FatFS/src/ffconf.h,./libraries/FatFS/src/ffsystem.cpp,./libraries/FatFS/src/ff.h,./libraries/lwIP_WINC1500/src/driver,./libraries/lwIP_WINC1500/src/common,./libraries/lwIP_WINC1500/src/bus_wrapper,./libraries/lwIP_WINC1500/src/spi_flash,./libraries/WiFi/examples/BearSSL_Validation/certs.h
        ignore_words_list: ser,dout,shiftIn,acount,froms
-    - name: Get submodules for following tests
-      run: git submodule update --init
-    - name: Check package references
-      run: |
-        ./tests/ci/pkgrefs_test.sh
    - name: Check boards.txt was not edited after makeboards.py
      run: |
        ./tools/makeboards.py
@@ -38,6 +33,15 @@ jobs:
        ./tests/restyle.sh
        # If anything changed, GIT should return an error and fail the test
        git diff --exit-code
+    - name: Check compiled PIO files
+      run: |
+        (cd ./tools && ./get.py)
+        ./tools/makepio.py
+        # If anything changed, GIT should return an error and fail the test
+        git diff -w --exit-code
+    - name: Check package references
+      run: |
+        ./tests/ci/pkgrefs_test.sh

 # Build all examples on linux (core and Arduino IDE)
  build-linux:
@@ -264,8 +268,8 @@ jobs:
      run: |
        python -m pip install --upgrade pip
        pip install --upgrade platformio
+        rm -rf ~/.platformio/platforms/raspberrypi*
        pio pkg install --global --platform https://github.com/maxgerhardt/platform-raspberrypi.git
-        pio pkg update --global --platform https://github.com/maxgerhardt/platform-raspberrypi.git
        pio pkg install --global --tool symlink://.
        cp -f /home/runner/work/arduino-pico/arduino-pico/tools/json/*.json /home/runner/.platformio/platforms/raspberrypi/boards/.
    - name: Build Multicore Example
@@ -321,8 +325,8 @@ jobs:
      run: |
        python -m pip install --upgrade pip
        pip install --upgrade platformio
+        rm -rf ~/.platformio/platforms/raspberrypi*
        pio pkg install --global --platform https://github.com/maxgerhardt/platform-raspberrypi.git
-        pio pkg update --global --platform https://github.com/maxgerhardt/platform-raspberrypi.git
        pio pkg install --global --tool symlink://.
        cp -f /home/runner/work/arduino-pico/arduino-pico/tools/json/*.json /home/runner/.platformio/platforms/raspberrypi/boards/.
    - name: Build Every Variant
@@ -5,5 +5,8 @@ docs/_build
 ota/build
 ota/build-rp2350
 ota/build-rp2350-riscv
-tools/libpico/build
+tools/libpico/boot
+tools/libpico/build-rp2040
+tools/libpico/build-rp2350
+tools/libpico/build-rp2350-riscv
 platform.local.txt
@@ -37,6 +37,7 @@ Read the [Contributing Guide](https://github.com/earlephilhower/arduino-pico/blo
 * Architeuthis Flux Jumperless V5
 * Arduino Nano RP2040 Connect
 * ArtronShop RP2 Nano
+* BIGTREETECH SKR-Pico
 * Breadstick Raspberry
 * BridgeTek IDM2040-7A
 * BridgeTek IDM2040-43A
@@ -69,16 +70,21 @@ Read the [Contributing Guide](https://github.com/earlephilhower/arduino-pico/blo
 * Melopero Cookie RP2040
 * Melopero Shake RP2040
 * METE HOCA Akana R1
+* Makerbase MKSTHR36
+* Makerbase MKSTHR42
 * MyMakers RP2040
 * Neko Systems BL2040 Mini
 * Newsan Archi
 * nullbits Bit-C PRO
+* Olimex Pico2XL
+* Olimex Pico2XXL
 * Olimex RP2040-Pico30
 * Pimoroni PGA2040
 * Pimoroni Pico Plus 2
 * Pimoroni Pico Plus 2W
 * Pimoroni Plasma2040
 * Pimoroni Plasma2350
+* Pimoroni Servo2040
 * Pimoroni Tiny2040
 * Pimoroni Tiny2350
 * Pintronix PinMax
@@ -93,11 +99,13 @@ Read the [Contributing Guide](https://github.com/earlephilhower/arduino-pico/blo
 * Solder Party RP2040 Stamp
 * Solder Party RP2350 Stamp
 * Solder Party RP2350 Stamp XL
+* SparkFun IoT RedBoard RP2350
 * SparkFun MicroMod RP2040
 * SparkFun ProMicro RP2040
 * SparkFun ProMicro RP2350
 * SparkFun Thing Plus RP2040
 * SparkFun Thing Plus RP2350
+* SparkFun XRP Controller
 * uPesy RP2040 DevKit
 * VCC-GND YD-RP2040
 * Viyalab Mizu RP2040
@@ -108,11 +116,15 @@ Read the [Contributing Guide](https://github.com/earlephilhower/arduino-pico/blo
 * Waveshare RP2040 LCD 1.28
 * Waveshare RP2040 Matrix
 * Waveshare RP2040 PiZero
+* Waveshare RP2350 Plus
+* Waveshare RP2350 LCD 0.96
 * WIZnet W5100S-EVB-Pico
 * WIZnet W5100S-EVB-Pico2
 * WIZnet W5500-EVB-Pico
 * WIZnet W5500-EVB-Pico2
 * WIZnet W55RP20-EVB-Pico
+* WIZnet W6300-EVB-Pico
+* WIZnet W6300-EVB-Pico2
 * WIZnet WizFi360-EVB-Pico
 * Generic RP2040 (configurable flash, I/O pins)
 * Generic RP2350 (configurable flash, I/O pins)
@@ -123,7 +135,7 @@ Read the [Contributing Guide](https://github.com/earlephilhower/arduino-pico/blo
 * Bluetooth Classic and BLE HID master mode (connect to BT keyboard, mouse, or joystick)
 * Generic Arduino USB Serial, Keyboard, Joystick, and Mouse emulation
 * WiFi (Pico W, ESP32-based ESPHost, Atmel WINC1500)
-* Ethernet (Wired WizNet W6100, WizNet W5500, WizNet W5100, ENC28J60)
+* Ethernet (Wired WizNet W6300, WizNet W6100, WizNet W5500, WizNet W5100, ENC28J60)
 * HTTP client and server (WebServer)
 * SSL/TLS/HTTPS
 * Over-the-Air (OTA) upgrades
@@ -27,10 +27,23 @@
 #include "RP2040Version.h"
 #include "api/ArduinoAPI.h"
 #include "api/itoa.h" // ARM toolchain doesn't provide itoa etc, provide them
+#include <pico.h>
+#undef PICO_RP2350A // Set in the RP2350 SDK boards file, overridden in the variant pins_arduino.h
 #include <pins_arduino.h>
 #include <hardware/gpio.h> // Required for the port*Register macros
 #include "debug_internal.h"

+// Chip sanity checking.  SDK uses interesting way of separating 2350A from 2350B, see https://github.com/raspberrypi/pico-sdk/issues/2364
+#if (!defined(PICO_RP2040) && !defined(PICO_RP2350)) || defined(PICO_RP2040) && defined(PICO_RP2350)
+#error Invalid core definition. Either PICO_RP2040 or PICO_RP2350 must be defined.
+#endif
+#if defined(PICO_RP2350) && !defined(PICO_RP2350A)
+#error Invalid RP2350 definition.  Need to set PICO_RP2350A=0/1 for A/B variant
+#endif
+#if defined(PICO_RP2350B)
+#error Do not define PICO_RP2350B.  Use PICO_RP2350A=0 to indicate RP2350B.  See the SDK for more details
+#endif
+
 // Try and make the best of the old Arduino abs() macro.  When in C++, use
 // the sane std::abs() call, but for C code use their macro since stdlib abs()
 // is int but their macro "works" for everything (with potential side effects)
@@ -152,7 +165,7 @@ constexpr uint64_t __bitset(const int (&a)[N], size_t i = 0U) {
 #define PSRAM __attribute__((section("\".psram\"")))

 // General GPIO/ADC layout info
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A
 #define __GPIOCNT 48
 #define __FIRSTANALOGGPIO 40
 #else
@@ -20,10 +20,21 @@

 #pragma once

+/**
+    @brief Wrapper class for polling the BOOTSEL button
+*/
 class __Bootsel {
 public:
    __Bootsel() { }
+    /**
+        @brief Get state of the BOOTSEL pin
+
+        @returns True if BOOTSEL pushed
+    */
    operator bool();
 };

+/**
+    @brief BOOTSEL accessor instance
+*/
 extern __Bootsel BOOTSEL;
@@ -1 +1,2 @@
 #include "api/IPAddress.h"
+using arduino::IPAddress;
@@ -53,16 +53,6 @@ bool PIOProgram::prepare(PIO *pio, int *sm, int *offset, int start, int cnt) {
    CoreMutex m(&_pioMutex);
    PIO pi[PIOCNT] = { PIOS };

-#if 0
-    uint usm;
-    uint uoff;
-    auto ret = pio_claim_free_sm_and_add_program_for_gpio_range(_pgm, pio, &usm, &uoff, start, cnt, true);
-    *sm = usm;
-    *offset = uoff;
-    DEBUGV("clain %d\n", ret);
-    return ret;
-#endif
-
    uint gpioBaseNeeded = ((start + cnt) >= 32) ? 16 : 0;
    DEBUGV("PIOProgram %p: Searching for base=%d, pins %d-%d\n", _pgm, gpioBaseNeeded, start, start + cnt - 1);

@@ -182,13 +182,16 @@ extern "C" void loop1() __attribute__((weak));
 extern "C" bool core1_separate_stack;
 extern "C" uint32_t* core1_separate_stack_address;

+/**
+    @brief RP2040/RP2350 helper function for HW-specific features
+*/
 class RP2040 {
 public:
    RP2040()  { /* noop */ }
    ~RP2040() { /* noop */ }

-    void begin() {
-        _epoch = 0;
+    void begin(int cpuid) {
+        _epoch[cpuid] = 0;
 #if !defined(__riscv) && !defined(__PROFILE)
        if (!__isFreeRTOS) {
            // Enable SYSTICK exception
@@ -197,43 +200,70 @@ public:
            systick_hw->rvr = 0x00FFFFFF;
        } else {
 #endif
-            int off = 0;
-            _ccountPgm = new PIOProgram(&ccount_program);
-            _ccountPgm->prepare(&_pio, &_sm, &off);
-            ccount_program_init(_pio, _sm, off);
-            pio_sm_set_enabled(_pio, _sm, true);
+            // Only start 1 instance of the PIO SM
+            if (cpuid == 0) {
+                int off = 0;
+                _ccountPgm = new PIOProgram(&ccount_program);
+                _ccountPgm->prepare(&_pio, &_sm, &off);
+                ccount_program_init(_pio, _sm, off);
+                pio_sm_set_enabled(_pio, _sm, true);
+            }
 #if !defined(__riscv) && !defined(__PROFILE)
        }
 #endif
    }

-    // Convert from microseconds to PIO clock cycles
+    /**
+        @brief Convert from microseconds to PIO clock cycles
+
+        @returns the PIO cycles for a given microsecond delay
+    */
    static int usToPIOCycles(int us) {
        // Parenthesis needed to guarantee order of operations to avoid 32bit overflow
        return (us * (clock_get_hz(clk_sys) / 1'000'000));
    }

-    // Get current clock frequency
+    /**
+        @brief Gets the active CPU speed (may differ from F_CPU
+
+        @returns CPU frequency in Hz
+    */
    static int f_cpu() {
        return clock_get_hz(clk_sys);
    }

-    // Get current CPU core number
+    /**
+        @brief Get the core ID that is currently executing this code
+
+        @returns 0 for Core 0, 1 for Core 1
+    */
    static int cpuid() {
        return sio_hw->cpuid;
    }

-    // Get CPU cycle count.  Needs to do magic to extens 24b HW to something longer
-    volatile uint64_t _epoch = 0;
+    /**
+        @brief CPU cycle counter epoch (24-bit cycle).  For internal use
+    */
+    volatile uint64_t _epoch[2] = {};
+    /**
+        @brief Get the count of CPU clock cycles since power on.
+
+        @details
+        The 32-bit count will overflow every 4 billion cycles, so consider using ``getCycleCount64`` for
+        longer measurements
+
+        @returns CPU clock cycles since power up
+    */
    inline uint32_t getCycleCount() {
 #if !defined(__riscv) && !defined(__PROFILE)
+        // Get CPU cycle count.  Needs to do magic to extend 24b HW to something longer
        if (!__isFreeRTOS) {
            uint32_t epoch;
            uint32_t ctr;
            do {
-                epoch = (uint32_t)_epoch;
+                epoch = (uint32_t)_epoch[sio_hw->cpuid];
                ctr = systick_hw->cvr;
-            } while (epoch != (uint32_t)_epoch);
+            } while (epoch != (uint32_t)_epoch[sio_hw->cpuid]);
            return epoch + (1 << 24) - ctr; /* CTR counts down from 1<<24-1 */
        } else {
 #endif
@@ -242,16 +272,20 @@ public:
        }
 #endif
    }
+    /**
+        @brief Get the count of CPU clock cycles since power on as a 64-bit quantrity

+        @returns CPU clock cycles since power up
+    */
    inline uint64_t getCycleCount64() {
 #if !defined(__riscv) && !defined(__PROFILE)
        if (!__isFreeRTOS) {
            uint64_t epoch;
            uint64_t ctr;
            do {
-                epoch = _epoch;
+                epoch = _epoch[sio_hw->cpuid];
                ctr = systick_hw->cvr;
-            } while (epoch != _epoch);
+            } while (epoch != _epoch[sio_hw->cpuid]);
            return epoch + (1LL << 24) - ctr;
        } else {
 #endif
@@ -261,23 +295,53 @@ public:
 #endif
    }

+    /**
+        @brief Gets total unused heap (dynamic memory)
+
+        @details
+        Note that the allocations of the size of the total free heap may fail due to fragmentation.
+        For example, ``getFreeHeap`` can report 100KB available, but an allocation of 90KB may fail
+        because there may not be a contiguous 90KB space available
+
+        @returns Free heap in bytes
+    */
    inline int getFreeHeap() {
        return getTotalHeap() - getUsedHeap();
    }

+    /**
+        @brief Gets total used heap (dynamic memory)
+
+        @returns Used heap in bytes
+    */
    inline int getUsedHeap() {
        struct mallinfo m = mallinfo();
        return m.uordblks;
    }

+    /**
+        @brief Gets total heap (dynamic memory) compiled into the program
+
+        @returns Total heap size in bytes
+    */
    inline int getTotalHeap() {
        return &__StackLimit  - &__bss_end__;
    }

+    /**
+        @brief On the RP2350, returns the amount of heap (dynamic memory) available in PSRAM
+
+        @returns Total free heap in PSRAM, or 0 if no PSRAM present
+    */
    inline int getFreePSRAMHeap() {
        return getTotalPSRAMHeap() - getUsedPSRAMHeap();
    }

+    /**
+        @brief On the RP2350, returns the total amount of PSRAM heap (dynamic memory) used
+
+        @returns Bytes used in PSRAM, or 0 if no PSRAM present
+    */
    inline int getUsedPSRAMHeap() {
 #if defined(RP2350_PSRAM_CS)
        extern size_t __psram_total_used();
@@ -287,6 +351,11 @@ public:
 #endif
    }

+    /**
+        @brief On the RP2350, gets total heap (dynamic memory) compiled into the program
+
+        @returns Total PSRAM heap size in bytes, or 0 if no PSRAM present
+    */
    inline int getTotalPSRAMHeap() {
 #if defined(RP2350_PSRAM_CS)
        extern size_t __psram_total_space();
@@ -296,6 +365,11 @@ public:
 #endif
    }

+    /**
+        @brief Gets the current stack pointer in a ARM/RISC-V safe manner
+
+        @returns Current SP
+    */
    inline uint32_t getStackPointer() {
        uint32_t *sp;
 #if defined(__riscv)
@@ -306,6 +380,14 @@ public:
        return (uint32_t)sp;
    }

+    /**
+        @brief Calculates approximately how much stack space is still available for the running core.  Handles multiprocessing and separate stacks.
+
+        @details
+        Not valid in FreeRTOS.  Use the FreeRTOS internal functions to access this information.
+
+        @returns Approximation of the amount of stack available for use on the specific core
+    */
    inline int getFreeStack() {
        const unsigned int sp = getStackPointer();
        uint32_t ref = 0x20040000;
@@ -319,6 +401,11 @@ public:
        return sp - ref;
    }

+    /**
+        @brief On the RP2350, gets the size of attached PSRAM
+
+        @returns PSRAM size in bytes, or 0 if no PSRAM present
+    */
    inline size_t getPSRAMSize() {
 #if defined(RP2350_PSRAM_CS)
        extern size_t __psram_size;
@@ -328,20 +415,48 @@ public:
 #endif
    }

+    /**
+        @brief Freezes the other core in a flash-write-safe state.  Not generally needed by applications
+
+        @details
+        When the external flash chip is erasing or writing, the Pico cannot fetch instructions from it.
+        In this case both the core doing the writing and the other core (if active) need to run from a
+        routine that's contained in RAM.  This call forces the other core into a tight, RAM-based loop
+        safe for this operation.  When flash erase/write is completed, ``resumeOtherCore`` to return
+        it to operation.
+
+        Be sure to disable any interrupts or task switches before calling to avoid deadlocks.
+
+        If the second core is not started, this is a no-op.
+    */
    void idleOtherCore() {
        fifo.idleOtherCore();
    }

+    /**
+        @brief Resumes normal operation of the other core
+    */
    void resumeOtherCore() {
        fifo.resumeOtherCore();
    }

+    /**
+        @brief Hard resets the 2nd core (CORE1).
+
+        @details
+        Because core1 will restart with the heap and global variables not in the same state as
+        power-on, this call may not work as desired and a full CPU reset may be necessary in
+        certain cases.
+    */
    void restartCore1() {
        multicore_reset_core1();
        fifo.clear();
        multicore_launch_core1(main1);
    }

+    /**
+        @brief Warm-reboots the chip in normal mode
+    */
    void reboot() {
        watchdog_reboot(0, 0, 10);
        while (1) {
@@ -349,10 +464,16 @@ public:
        }
    }

+    /**
+        @brief Warm-reboots the chip in normal mode
+    */
    inline void restart() {
        reboot();
    }

+    /**
+        @brief Warm-reboots the chip into the USB bootloader mode
+    */
    inline void rebootToBootloader() {
        reset_usb_boot(0, 0);
        while (1) {
@@ -364,16 +485,32 @@ public:
    static void enableDoubleResetBootloader();
 #endif

+    /**
+        @brief Starts the hardware watchdog timer.  The CPU will reset if the watchdog is not fed every delay_ms
+
+        @param [in] delay_ms Milliseconds without a wdt_reset before rebooting
+    */
    void wdt_begin(uint32_t delay_ms) {
        watchdog_enable(delay_ms, 1);
    }

+    /**
+        @brief Feeds the watchdog timer, resetting it for another delay_ms countdown
+    */
    void wdt_reset() {
        watchdog_update();
    }

+    /**
+        @brief Best-effort reasons for chip reset
+    */
    enum resetReason_t {UNKNOWN_RESET, PWRON_RESET, RUN_PIN_RESET, SOFT_RESET, WDT_RESET, DEBUG_RESET, GLITCH_RESET, BROWNOUT_RESET};

+    /**
+        @brief Attempts to determine the reason for the last chip reset.  May not always be able to determine accurately
+
+        @returns Reason for reset
+    */
    resetReason_t getResetReason(void) {
        io_rw_32 *WD_reason_reg = (io_rw_32 *)(WATCHDOG_BASE + WATCHDOG_REASON_OFFSET);

@@ -427,6 +564,10 @@ public:
        return UNKNOWN_RESET;
    }

+    /**
+        @brief Get unique ID string for the running board
+        @returns String with the unique board ID as determined by the SDK
+    */
    const char *getChipID() {
        static char id[2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1] = { 0 };
        if (!id[0]) {
@@ -437,6 +578,17 @@ public:

 #pragma GCC push_options
 #pragma GCC optimize ("Os")
+    /**
+        @brief Perform a memcpy using a DMA engine for speed
+
+        @details
+        Uses the DMA to copy to and from RAM.  Only works on 4-byte aligned, 4-byte multiple length
+        sources and destination (i.e. word-aligned, word-length).  Falls back to normal memcpy otherwise.
+
+        @param [out] dest Memcpy destination, 4-byte aligned
+        @param [in] src Memcpy source, 4-byte aligned
+        @param [in] n Count in bytes to transfer (should be a multiple of 4 bytes)
+    */
    void *memcpyDMA(void *dest, const void *src, size_t n) {
        // Allocate a DMA channel on 1st call, reuse it every call after
        if (memcpyDMAChannel < 1) {
@@ -465,14 +617,32 @@ public:
    }
 #pragma GCC pop_options

-    // Multicore comms FIFO
+    /**
+        @brief Multicore communications FIFO
+    */
    _MFIFO fifo;


+    /**
+        @brief Return a 32-bit from the hardware random number generator
+
+        @returns Random value using appropriate hardware (RP2350 has true RNG, RP2040 has a less true RNG method)
+    */
    uint32_t hwrand32() {
        return get_rand_32();
    }

+    /**
+        @brief Determines if code is running on a Pico or a PicoW
+
+        @details
+        Code compiled for the RP2040 PicoW can run on the RP2040 Pico.  This call lets an application
+        identify if the current device is really a Pico or PicoW and handle appropriately.  For
+        the RP2350, this runtime detection is not available and the call returns whether it was
+        compiled for the CYW43 WiFi driver
+
+        @returns True if running on a PicoW board with CYW43 WiFi chip.
+    */
    bool isPicoW() {
 #if !defined(PICO_CYW43_SUPPORTED)
        return false;
@@ -499,8 +669,8 @@ public:


 private:
-    static void _SystickHandler() {
-        rp2040._epoch += 1LL << 24;
+    static void __no_inline_not_in_flash_func(_SystickHandler)() {
+        rp2040._epoch[sio_hw->cpuid] += 1LL << 24;
    }
    PIO _pio;
    int _sm;
@@ -1,5 +1,5 @@
 #pragma once
 #define ARDUINO_PICO_MAJOR 4
-#define ARDUINO_PICO_MINOR 4
-#define ARDUINO_PICO_REVISION 4
-#define ARDUINO_PICO_VERSION_STR "4.4.4"
+#define ARDUINO_PICO_MINOR 6
+#define ARDUINO_PICO_REVISION 0
+#define ARDUINO_PICO_VERSION_STR "4.6.0"
@@ -24,7 +24,9 @@

 // Input/output will be handled by OpenOCD

-// From https://developer.arm.com/documentation/dui0471/g/Semihosting/Semihosting-operations?lang=en
+/**
+    @brief Semihosting host API opcodes, from https://developer.arm.com/documentation/dui0471/g/Semihosting/Semihosting-operations?lang=en
+*/
 typedef enum {
    SEMIHOST_SYS_CLOSE = 0x02,
    SEMIHOST_SYS_CLOCK = 0x10,
@@ -52,7 +54,13 @@ typedef enum {

 #ifdef __arm__

-// From https://github.com/ErichStyger/mcuoneclipse/blob/master/Examples/MCUXpresso/FRDM-K22F/FRDM-K22F_Semihosting/source/McuSemihost.c
+/**
+    @brief Execute a semihosted request, from https://github.com/ErichStyger/mcuoneclipse/blob/master/Examples/MCUXpresso/FRDM-K22F/FRDM-K22F_Semihosting/source/McuSemihost.c
+
+    @param [in] reason Opcode to execute
+    @param [in] arg Any arguments for the opcode
+    @returns Result of operation
+*/
 static inline int __attribute__((always_inline)) Semihost(int reason, void *arg) {
    int value;
    __asm volatile(
@@ -69,7 +77,13 @@ static inline int __attribute__((always_inline)) Semihost(int reason, void *arg)
 }
 #else

-// https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/n-5VQ9PHZ4w/m/KbzH5t9MBgAJ
+/**
+    @brief Execute a semihosted request, from https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/n-5VQ9PHZ4w/m/KbzH5t9MBgAJ
+
+    @param [in] reason Opcode to execute
+    @param [in] argPack Any arguments for the opcode
+    @returns Result of operation
+*/
 static inline int __attribute__((always_inline)) Semihost(int reason, void *argPack) {
    register int value asm("a0") = reason;
    register void *ptr asm("a1") = argPack;
@@ -68,13 +68,10 @@ static PIOProgram *_getRxProgram(int bits) {
 }
 // ------------------------------------------------------------------------

-// TODO - this works, but there must be a faster/better way...
-static int _parity(int bits, int data) {
-    int p = 0;
-    for (int b = 0; b < bits; b++) {
-        p ^= (data & (1 << b)) ? 1 : 0;
-    }
-    return p;
+static int __not_in_flash_func(_parity)(int data) {
+    data ^= data >> 4;
+    data &= 0xf;
+    return (0x6996 >> data) & 1;
 }

 // We need to cache generated SerialPIOs so we can add data to them from
@@ -98,20 +95,16 @@ void __not_in_flash_func(SerialPIO::_handleIRQ)() {
    }
    while (!pio_sm_is_rx_fifo_empty(_rxPIO, _rxSM)) {
        uint32_t decode = _rxPIO->rxf[_rxSM];
-        decode >>= 33 - _rxBits;
-        uint32_t val = 0;
-        for (int b = 0; b < _bits + 1; b++) {
-            val |= (decode & (1 << (b * 2))) ? 1 << b : 0;
-        }
+        uint32_t val = decode >> (32 - _rxBits - 1);
        if (_parity == UART_PARITY_EVEN) {
-            int p = ::_parity(_bits, val);
+            int p = ::_parity(val);
            int r = (val & (1 << _bits)) ? 1 : 0;
            if (p != r) {
                // TODO - parity error
                continue;
            }
        } else if (_parity == UART_PARITY_ODD) {
-            int p = ::_parity(_bits, val);
+            int p = ::_parity(val);
            int r = (val & (1 << _bits)) ? 1 : 0;
            if (p == r) {
                // TODO - parity error
@@ -234,7 +227,7 @@ void SerialPIO::begin(unsigned long baud, uint16_t config) {
        _writer = 0;
        _reader = 0;

-        _rxBits = 2 * (_bits + _stop + (_parity != UART_PARITY_NONE ? 1 : 0) + 1) - 1;
+        _rxBits = _bits + (_parity != UART_PARITY_NONE ? 1 : 0);
        _rxPgm = _getRxProgram(_rxBits);
        int off;
        if (!_rxPgm->prepare(&_rxPIO, &_rxSM, &off, _rx, 1)) {
@@ -249,7 +242,7 @@ void SerialPIO::begin(unsigned long baud, uint16_t config) {
        pio_sm_clear_fifos(_rxPIO, _rxSM); // Remove any existing data

        // Put phase divider into OSR w/o using add'l program memory
-        pio_sm_put_blocking(_rxPIO, _rxSM, clock_get_hz(clk_sys) / (_baud * 2) - 7 /* insns in PIO halfbit loop */);
+        pio_sm_put_blocking(_rxPIO, _rxSM, clock_get_hz(clk_sys) / (_baud * 2) - 3);
        pio_sm_exec(_rxPIO, _rxSM, pio_encode_pull(false, false));

        // Join the TX FIFO to the RX one now that we don't need it
@@ -378,10 +371,10 @@ size_t SerialPIO::write(uint8_t c) {
    if (_parity == UART_PARITY_NONE) {
        val |= 7 << _bits; // Set 2 stop bits, the HW will only transmit the required number
    } else if (_parity == UART_PARITY_EVEN) {
-        val |= ::_parity(_bits, c) << _bits;
+        val |= ::_parity(c) << _bits;
        val |= 7 << (_bits + 1);
    } else {
-        val |= (1 ^ ::_parity(_bits, c)) << _bits;
+        val |= (1 ^ ::_parity(c)) << _bits;
        val |= 7 << (_bits + 1);
    }
    val <<= 1;  // Start bit = low
@@ -32,15 +32,20 @@ extern void serialEvent1() __attribute__((weak));
 extern void serialEvent2() __attribute__((weak));

 bool SerialUART::setRX(pin_size_t pin) {
-#ifdef PICO_RP2350B
-    constexpr uint64_t valid[2] = { __bitset({1, 13, 17, 29, 33, 45}) /* UART0 */,
-                                    __bitset({5, 9, 21, 25, 37, 41})  /* UART1 */
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
+    constexpr uint64_t valid[2] = { __bitset({1, 3, 13, 15, 17, 19, 29, 31, 33, 35, 45, 47}) /* UART0 */,
+                                    __bitset({5, 7, 9, 11, 21, 23, 25, 27, 37, 39, 41, 43})  /* UART1 */
+                                  };
+#elif defined(PICO_RP2350)
+    constexpr uint64_t valid[2] = { __bitset({1, 3, 13, 15, 17, 19, 29})     /* UART0 */,
+                                    __bitset({5, 7, 9, 11, 21, 23, 25, 27})  /* UART1 */
                                  };
 #else
    constexpr uint64_t valid[2] = { __bitset({1, 13, 17, 29}) /* UART0 */,
                                    __bitset({5, 9, 21, 25})  /* UART1 */
                                  };
 #endif
+
    if ((!_running) && ((1LL << pin) & valid[uart_get_index(_uart)])) {
        _rx = pin;
        return true;
@@ -59,9 +64,13 @@ bool SerialUART::setRX(pin_size_t pin) {
 }

 bool SerialUART::setTX(pin_size_t pin) {
-#ifdef PICO_RP2350B
-    constexpr uint64_t valid[2] = { __bitset({0, 12, 16, 28, 32, 44}) /* UART0 */,
-                                    __bitset({4, 8, 20, 24, 36, 40})  /* UART1 */
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
+    constexpr uint64_t valid[2] = { __bitset({0, 2, 12, 14, 16, 18, 28, 30, 32, 34, 44, 46}) /* UART0 */,
+                                    __bitset({4, 6, 8, 10, 20, 22, 24, 26, 36, 38, 40, 42})  /* UART1 */
+                                  };
+#elif defined(PICO_RP2350)
+    constexpr uint64_t valid[2] = { __bitset({0, 2, 12, 14, 16, 18, 28})     /* UART0 */,
+                                    __bitset({4, 6, 8, 10, 20, 22, 24, 26})  /* UART1 */
                                  };
 #else
    constexpr uint64_t valid[2] = { __bitset({0, 12, 16, 28}) /* UART0 */,
@@ -86,7 +95,7 @@ bool SerialUART::setTX(pin_size_t pin) {
 }

 bool SerialUART::setRTS(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({3, 15, 19, 31, 35, 47}) /* UART0 */,
                                    __bitset({7, 11, 23, 27, 39, 43})  /* UART1 */
                                  };
@@ -113,7 +122,7 @@ bool SerialUART::setRTS(pin_size_t pin) {
 }

 bool SerialUART::setCTS(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({2, 14, 18, 30, 34, 46}) /* UART0 */,
                                    __bitset({6, 10, 22, 26, 38, 42})  /* UART1 */
                                  };
@@ -170,6 +179,41 @@ SerialUART::SerialUART(uart_inst_t *uart, pin_size_t tx, pin_size_t rx, pin_size
 static void _uart0IRQ();
 static void _uart1IRQ();

+// Does the selected TX/RX need UART_AUX function (rp2350)
+static gpio_function_t __gpioFunction(int pin) {
+    switch (pin) {
+#if defined(PICO_RP2350) && !PICO_RP2350A
+    case 2:
+    case 3:
+    case 6:
+    case 7:
+    case 10:
+    case 11:
+    case 14:
+    case 15:
+    case 18:
+    case 19:
+    case 22:
+    case 23:
+    case 26:
+    case 27:
+    case 30:
+    case 31:
+    case 34:
+    case 35:
+    case 38:
+    case 39:
+    case 42:
+    case 43:
+    case 46:
+    case 47:
+        return GPIO_FUNC_UART_AUX;
+#endif
+    default:
+        return GPIO_FUNC_UART;
+    }
+}
+
 void SerialUART::begin(unsigned long baud, uint16_t config) {
    if (_running) {
        end();
@@ -180,9 +224,9 @@ void SerialUART::begin(unsigned long baud, uint16_t config) {

    _fcnTx = gpio_get_function(_tx);
    _fcnRx = gpio_get_function(_rx);
-    gpio_set_function(_tx, GPIO_FUNC_UART);
+    gpio_set_function(_tx, __gpioFunction(_tx));
    gpio_set_outover(_tx, _invertTX ? 1 : 0);
-    gpio_set_function(_rx, GPIO_FUNC_UART);
+    gpio_set_function(_rx, __gpioFunction(_rx));
    gpio_set_inover(_rx, _invertRX ? 1 : 0);
    if (_rts != UART_PIN_NOT_DEFINED) {
        _fcnRts = gpio_get_function(_rts);
@@ -22,9 +22,18 @@

 #include "SerialPIO.h"

+/**
+    @brief Implements a UART port using PIO for input and output
+*/
 class SoftwareSerial : public SerialPIO {
 public:
-    // Note the rx/tx pins are swapped in PIO vs SWSerial
+    /**
+        @brief Constructs a PIO-based UART
+
+        @param [in] rx GPIO for RX pin or -1 for transmit-only
+        @param [in] tx GPIO for TX pin or -1 for receive-only
+        @param [in] invert True to invert the receive and transmit lines
+    */
    SoftwareSerial(pin_size_t rx, pin_size_t tx, bool invert = false) : SerialPIO(tx, rx) {
        _invert = invert;
    }
@@ -32,18 +41,37 @@ public:
    ~SoftwareSerial() {
    }

+    /**
+        @brief Starts the PIO UART
+
+        @param [in] baud Serial bit rate
+    */
    virtual void begin(unsigned long baud = 115200) override {
        begin(baud, SERIAL_8N1);
    };

+    /**
+        @brief Starts the PIO UART
+
+        @param [in] baud Serial bit rate
+        @param [in] config Start/Stop/Len configuration (i.e. SERIAL_8N1 or SERIAL_7E2)
+    */
    void begin(unsigned long baud, uint16_t config) override {
        setInvertTX(_invert);
        setInvertRX(_invert);
        SerialPIO::begin(baud, config);
    }

+    /**
+        @brief No-op on this core
+    */
    void listen() { /* noop */ }

+    /**
+        @brief No-op on this core
+
+        @returns True always
+    */
    bool isListening() {
        return true;
    }
@@ -28,7 +28,7 @@ static const struct pio_program ccount_program = {
    .instructions = ccount_program_instructions,
    .length = 2,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = ccount_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -22,7 +22,11 @@
 #include "RP2040USB.h"
 #include <pico/stdlib.h>
 #include <pico/multicore.h>
+#include <hardware/vreg.h>
 #include <reent.h>
+#ifdef RP2350_PSRAM_CS
+#include "psram.h"
+#endif

 RP2040 rp2040;
 extern "C" {
@@ -47,9 +51,14 @@ void initVariant() { }

 // Optional 2nd core setup and loop
 bool core1_separate_stack __attribute__((weak)) = false;
+bool core1_disable_systick __attribute__((weak)) = false;
 extern void setup1() __attribute__((weak));
 extern void loop1() __attribute__((weak));
 extern "C" void main1() {
+    if (!core1_disable_systick) {
+        // Don't install the SYSTICK exception handler. rp2040.getCycleCount will not work properly on core1
+        rp2040.begin(1);
+    }
    rp2040.fifo.registerCore();
    if (setup1) {
        setup1();
@@ -80,9 +89,41 @@ static struct _reent *_impure_ptr1 = nullptr;

 extern "C" int main() {
 #if (defined(PICO_RP2040) && (F_CPU != 125000000)) || (defined(PICO_RP2350) && (F_CPU != 150000000))
-    set_sys_clock_khz(F_CPU / 1000, true);
+
+#if defined(PICO_RP2040)
+    // From runtime_init_clocks() to bump up RP2040 V for 200Mhz+ operation
+    if ((F_CPU > 133000000) && (vreg_get_voltage() < VREG_VOLTAGE_1_15)) {
+        vreg_set_voltage(VREG_VOLTAGE_1_15);
+        // wait for voltage to settle; must use CPU cycles as TIMER is not yet clocked correctly
+        busy_wait_at_least_cycles((uint32_t)((SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US * (uint64_t)XOSC_HZ) / 1000000));
+    }
 #endif

+#if defined(RP2350_PSRAM_CS) && (F_CPU > 150000000)
+    // Need to increase the qmi divider before upping sysclk to ensure we keep the output sck w/in legal bounds
+    psram_reinit_timing(F_CPU);
+    // Per datasheet, need to do a dummy access and memory barrier before it takes effect
+    extern uint8_t __psram_start__;
+    volatile uint8_t *x = &__psram_start__;
+    *x ^= 0xff;
+    *x ^= 0xff;
+    asm volatile("" ::: "memory");
+#endif
+
+    set_sys_clock_khz(F_CPU / 1000, true);
+
+#if defined(RP2350_PSRAM_CS) && (F_CPU < 150000000)
+    psram_reinit_timing();
+    // Per datasheet, need to do a dummy access and memory barrier before it takes effect
+    extern uint8_t __psram_start__;
+    volatile uint8_t *x = &__psram_start__;
+    *x ^= 0xff;
+    *x ^= 0xff;
+    asm volatile("" ::: "memory");
+#endif
+
+#endif // over/underclock
+
    // Let rest of core know if we're using FreeRTOS
    __isFreeRTOS = initFreeRTOS ? true : false;

@@ -92,7 +133,7 @@ extern "C" int main() {
        _REENT_INIT_PTR(_impure_ptr1);
    }

-    rp2040.begin();
+    rp2040.begin(0);

    initVariant();

@@ -203,3 +244,10 @@ void hexdump(const void* mem, uint32_t len, uint8_t cols) {
 }

 const String emptyString = "";
+
+extern "C" void __attribute__((__noreturn__)) __wrap___stack_chk_fail() {
+    while (true) {
+        panic("*** stack smashing detected ***: terminated\n");
+    }
+}
+
@@ -73,20 +73,25 @@ static inline void pio_tx_program_init(PIO pio, uint sm, uint offset, uint pin_t
 ; IN pin 0 and JMP pin are both mapped to the GPIO used as UART RX.

 start:
-    set x, 18           ; Preload bit counter...we'll shift in the start bit and stop bit, and each bit will be double-recorded (to be fixed by RP2040 code)
+    set x, 18           ; Preload bit counter...overwritten by the app
    wait 0 pin 0        ; Stall until start bit is asserted

-bitloop:
   ; Delay until 1/2 way into the bit time
    mov y, osr
-wait_half:
-    jmp y-- wait_half
+wait_mid_start:
+    jmp y-- wait_mid_start

-    ; Read in the bit
-    in pins, 1          ; Shift data bit into ISR
-    jmp x-- bitloop     ; Loop all bits
-    
-    push                ; Stuff it and wait for next start
+bitloop:
+    mov y, osr
+bitloop1:
+    jmp y-- bitloop1
+    mov y, osr
+bitloop2:
+    jmp y-- bitloop2
+
+    in pins, 1
+    jmp x-- bitloop
+    push

 % c-sdk {
 static inline void pio_rx_program_init(PIO pio, uint sm, uint offset, uint pin) {
@@ -32,7 +32,7 @@ static const struct pio_program pio_tx_program = {
    .instructions = pio_tx_program_instructions,
    .length = 6,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_tx_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -71,7 +71,7 @@ static inline void pio_tx_program_init(PIO pio, uint sm, uint offset, uint pin_t
 // ------ //

 #define pio_rx_wrap_target 0
-#define pio_rx_wrap 6
+#define pio_rx_wrap 10
 #define pio_rx_pio_version 0

 static const uint16_t pio_rx_program_instructions[] = {
@@ -80,18 +80,22 @@ static const uint16_t pio_rx_program_instructions[] = {
    0x2020, //  1: wait   0 pin, 0
    0xa047, //  2: mov    y, osr
    0x0083, //  3: jmp    y--, 3
-    0x4001, //  4: in     pins, 1
-    0x0042, //  5: jmp    x--, 2
-    0x8020, //  6: push   block
+    0xa047, //  4: mov    y, osr
+    0x0085, //  5: jmp    y--, 5
+    0xa047, //  6: mov    y, osr
+    0x0087, //  7: jmp    y--, 7
+    0x4001, //  8: in     pins, 1
+    0x0044, //  9: jmp    x--, 4
+    0x8020, // 10: push   block
    //     .wrap
 };

 #if !PICO_NO_HARDWARE
 static const struct pio_program pio_rx_program = {
    .instructions = pio_rx_program_instructions,
-    .length = 7,
+    .length = 11,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_rx_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -195,10 +195,7 @@ static size_t __no_inline_not_in_flash_func(get_psram_size)(void) {
 ///
 /// @note This function expects interrupts to be enabled on entry

-static void __no_inline_not_in_flash_func(set_psram_timing)(void) {
-    // Get secs / cycle for the system clock - get before disabling interrupts.
-    uint32_t sysHz = (uint32_t)clock_get_hz(clk_sys);
-
+static void __no_inline_not_in_flash_func(set_psram_timing)(uint32_t sysHz) {
    // Calculate the clock divider - goal to get clock used for PSRAM <= what
    // the PSRAM IC can handle - which is defined in SFE_PSRAM_MAX_SCK_HZ
    volatile uint8_t clockDivider = (sysHz + SFE_PSRAM_MAX_SCK_HZ - 1) / SFE_PSRAM_MAX_SCK_HZ;
@@ -283,7 +280,7 @@ static void __no_inline_not_in_flash_func(runtime_init_setup_psram)(/*uint32_t p

    // check our interrupts and setup the timing
    restore_interrupts(intr_stash);
-    set_psram_timing();
+    set_psram_timing((uint32_t)clock_get_hz(clk_sys));

    // and now stash interrupts again
    intr_stash = save_and_disable_interrupts();
@@ -323,8 +320,11 @@ static void __no_inline_not_in_flash_func(runtime_init_setup_psram)(/*uint32_t p
 PICO_RUNTIME_INIT_FUNC_RUNTIME(runtime_init_setup_psram, PICO_RUNTIME_INIT_PSRAM);

 // update timing -- used if the system clock/timing was changed.
-void psram_reinit_timing() {
-    set_psram_timing();
+void psram_reinit_timing(uint32_t hz) {
+    if (!hz) {
+        hz = (uint32_t)clock_get_hz(clk_sys);
+    }
+    set_psram_timing(hz);
 }

 static bool __psram_heap_init() {
@@ -31,7 +31,7 @@

 #include <Arduino.h>

-void psram_reinit_timing();
+void psram_reinit_timing(uint32_t hz = 0);
 void *__psram_malloc(size_t size);
 void __psram_free(void *ptr);
 void *__psram_realloc(void *ptr, size_t size);
@@ -17,14 +17,14 @@
 #define tone2_pio_version 0

 static const uint16_t tone2_program_instructions[] = {
-    //         .wrap_target
+    //     .wrap_target
    0x8080, //  0: pull   noblock
    0xb827, //  1: mov    x, osr          side 1
    0xa047, //  2: mov    y, osr
    0x0083, //  3: jmp    y--, 3
    0xb047, //  4: mov    y, osr          side 0
    0x0085, //  5: jmp    y--, 5
-    //         .wrap
+    //     .wrap
 };

 #if !PICO_NO_HARDWARE
@@ -12,9 +12,9 @@ need to be periodically sampled to be read by applications, easily, such as:
 * Light dependent resistors (LDR), etc.


-Up to 4 analog samples can be recorded by the hardware (``A0`` ... ``A3``), and all
-recording is done at 16-bit levels (but be aware that the ADC in the Pico will only
-ever return values between 0...4095).
+Up to 4 (or 8 in the case of the RP2350B) analog samples can be recorded by the
+hardware (``A0`` ... ``A3``), and all recording is done at 16-bit levels (but be
+aware that the ADC in the Pico will only ever return values between 0...4095).

 The interface for the ``ADCInput`` device is very similar to the ``I2S`` input
 device, and most code can be ported simply by instantiating a ``ADCInput``
@@ -26,11 +26,12 @@ allowed while in use.
 ADC Input API
 -------------

-ADCInput(pin0 [, pin1, pin2, pin3])
+ADCInput(pin0 [, pin1, pin2, pin3[, pin4, pin5, pin6, pin7])
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 Creates an ADC input object which will record the pins specified in the code.
-Only pins ``A0`` ... ``A3`` can be used, and they must be specified in increasing
-order (i.e. ``ADCInput(A0, A1);`` is valid, but ``ADCInput(A1, A0)`` is not.
+Only pins ``A0`` ... ``A3`` (``A7`` on RP2350B) can be used, and they must be
+specified in increasing order (i.e. ``ADCInput(A0, A1);`` is valid,
+but ``ADCInput(A1, A0)`` is not.

 bool setBuffers(size_t buffers, size_t bufferWords)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -54,9 +54,9 @@ author = u'Earle F. Philhower, III'
 # built documents.
 #
 # The short X.Y version.
-version = u'4.4.4'
+version = u'4.6.0'
 # The full version, including alpha/beta/rc tags.
-release = u'4.4.4'
+release = u'4.6.0'

 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.
@@ -112,7 +112,7 @@ For only RP2350A variants (using the compile options, not the onboard ID registe

 .. code:: cpp

-    #if defined(PICO_RP2350) && !defined(PICO_RP2350B)
+    #if defined(PICO_RP2350A) && PICO_RP2350A
    ...RP2350A only code...
    #endif

@@ -121,7 +121,7 @@ and not the chip ID register):

 .. code:: cpp

-    #if defined(PICO_RP2350B)
+    #if defined(PICO_RP2350A) && !PICO_RP2350A
    ...48-GPIO version code here
    #endif

@@ -16,6 +16,25 @@ not necessarily simultaneously!).
 See the ``Multicore.ino`` example in the ``rp2040`` example directory for a
 quick introduction.

+Core 1 Operation
+----------------
+
+By default, core1 (the second core) has no non-user written code running on it.
+No interrupts, exceptions, or other background processing is done (but the core
+is still subject to hardware stalls due to on-die memory resource conflicts).
+When flash erase or write operations (i.e. ``LittleFS`` or ``EEPROM``) are called
+from core0, core1 **will** be paused.
+
+If ``rp2040.getCycleCount`` is needed to operate on the second core, then a
+periodic (once ever 16M clock cycles) ``SYSTICK`` exception will happen behind
+the scenes.  For extremely time-critical operations this may not be desirable
+and can be disabled by defining a new ``bool`` variable to ``true`` anywhere
+in your sketch:
+
+.. code:: cpp
+
+    bool core1_disable_systick = true;
+
 Stack Sizes
 -----------

@@ -67,6 +86,9 @@ void rp2040.restartCore1()
 ~~~~~~~~~~~~~~~~~~~~~~~~~~

 Hard resets Core1 from Core 0 and restarts its operation from ``setup1()``.
+This can cause unpredictable behavior because globals and the heap
+are shared between cores and not re-initialized with this call.  Use with
+extreme caution.

 Communicating Between Cores
 ---------------------------
@@ -1,2 +1,2 @@
 // Do not edit -- Automatically generated by tools/sdk/ssl/bearssl/Makefile
-#define BEARSSL_GIT 5b7f3d5
+#define BEARSSL_GIT aca1383
@@ -13,7 +13,7 @@

 #define PICO_SDK_VERSION_MAJOR    2
 #define PICO_SDK_VERSION_MINOR    1
-#define PICO_SDK_VERSION_REVISION 0
-#define PICO_SDK_VERSION_STRING   "2.1.0"
+#define PICO_SDK_VERSION_REVISION 2
+#define PICO_SDK_VERSION_STRING   "2.1.2-develop"

 #endif
@@ -13,7 +13,7 @@

 #define PICO_SDK_VERSION_MAJOR    2
 #define PICO_SDK_VERSION_MINOR    1
-#define PICO_SDK_VERSION_REVISION 0
-#define PICO_SDK_VERSION_STRING   "2.1.0"
+#define PICO_SDK_VERSION_REVISION 2
+#define PICO_SDK_VERSION_STRING   "2.1.2-develop"

 #endif
@@ -54,6 +54,7 @@
 -iwithprefixbefore/pico-sdk/src/rp2_common/pico_lwip/include
 -iwithprefixbefore/pico-sdk/src/rp2_common/pico_multicore/include
 -iwithprefixbefore/pico-sdk/src/rp2_common/pico_platform/include
+-iwithprefixbefore/pico-sdk/src/rp2_common/pico_platform_common/include
 -iwithprefixbefore/pico-sdk/src/rp2_common/pico_platform_compiler/include
 -iwithprefixbefore/pico-sdk/src/rp2_common/pico_platform_sections/include
 -iwithprefixbefore/pico-sdk/src/rp2_common/pico_platform_panic/include
@@ -67,3 +67,5 @@
 -Wl,--wrap=cyw43_tcpip_link_status
 -Wl,--wrap=cyw43_cb_tcpip_init
 -Wl,--wrap=cyw43_cb_tcpip_deinit
+
+-Wl,--wrap=__stack_chk_fail
@@ -10,5 +10,6 @@
 -iwithprefixbefore/pico-sdk/lib/btstack/src
 -iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/bluedroid/decoder/include
 -iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/bluedroid/encoder/include
+-iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/yxml
 -iwithprefixbefore/pico-sdk/lib/btstack/platform/embedded
 -iwithprefixbefore/pico-sdk/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include
@@ -1,4 +1,5 @@
 -DPICO_CYW43_ARCH_THREADSAFE_BACKGROUND=1
+-DTARGET_RP2350
 -DCYW43_LWIP=1
 -DCYW43_PIO_CLOCK_DIV_DYNAMIC=1
 -DCFG_TUSB_MCU=OPT_MCU_RP2040
@@ -15,4 +15,5 @@
 -iwithprefixbefore/pico-sdk/lib/btstack/src
 -iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/bluedroid/decoder/include
 -iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/bluedroid/encoder/include
+-iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/yxml
 -iwithprefixbefore/pico-sdk/lib/btstack/platform/embedded
@@ -1,4 +1,5 @@
 -DPICO_CYW43_ARCH_THREADSAFE_BACKGROUND=1
+-DTARGET_RP2350
 -DCYW43_LWIP=1
 -DCYW43_PIO_CLOCK_DIV_DYNAMIC=1
 -DCFG_TUSB_MCU=OPT_MCU_RP2040
@@ -13,4 +13,5 @@
 -iwithprefixbefore/pico-sdk/lib/btstack/src
 -iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/bluedroid/decoder/include
 -iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/bluedroid/encoder/include
+-iwithprefixbefore/pico-sdk/lib/btstack/3rd-party/yxml
 -iwithprefixbefore/pico-sdk/lib/btstack/platform/embedded
@@ -23,6 +23,7 @@
 #include <Arduino.h>
 #include "ADCInput.h"
 #include <hardware/adc.h>
+#include <debug_internal.h>

 ADCInput::ADCInput(pin_size_t p0, pin_size_t p1, pin_size_t p2, pin_size_t p3, pin_size_t p4, pin_size_t p5, pin_size_t p6, pin_size_t p7) {
    _running = false;
@@ -49,12 +50,7 @@ bool ADCInput::setBuffers(size_t buffers, size_t bufferWords) {

 int ADCInput::_mask(pin_size_t p) {
    switch (p) {
-#if !defined(PICO_RP2350B)
-    case 26: return 1;
-    case 27: return 2;
-    case 28: return 4;
-    case 29: return 8;
-#else // Starts at 40 and there are 8 of them
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    case 40: return 1;
    case 41: return 2;
    case 42: return 4;
@@ -63,6 +59,11 @@ int ADCInput::_mask(pin_size_t p) {
    case 45: return 32;
    case 46: return 64;
    case 47: return 128;
+#else
+    case 26: return 1;
+    case 27: return 2;
+    case 28: return 4;
+    case 29: return 8;
 #endif
    default: return 0;
    }
@@ -106,7 +107,7 @@ bool ADCInput::begin() {
    // Set up the GPIOs to go to ADC
    adc_init();
    int cnt = 0;
-#if !defined(PICO_RP2350B)
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    int startpin = 26;
    int maxpin = 29;
 #else
@@ -122,6 +123,18 @@ bool ADCInput::begin() {
            adc_gpio_init(pin);
        }
    }
+
+    // Make sure the bufferWords is a multiple of the natural size.
+    // For 1 and 2 inputs there will never be a misalignment on overflow
+    // For 3 inputs we need to have a multiple of 3 words to guarantee that every buffer[0] is ADC[0].  OTW we can slip on an overflow
+    // Data = [ADC0:ADC1, ADC2:ADC0, ADC1:ADC2], [ADC0:ADC1, ADC2:ADC0, ADC1:ADC2,ADC3], ...
+    // For 4 inputs we need to have a multiple of 2 words, same reason.  See #2991
+    // Data = [ADC0:ADC1, ADC2:ADC3] [ADC0:ADC1, ADC2:ADC3]
+    if (((cnt == 3) && (_bufferWords % 3)) || ((cnt == 4) && (_bufferWords % 2))) {
+        DEBUGV("ADCInput: bufferWords needs to be a multiple of 3 for 3 inputs, 2 for 4 inputs\n");
+        return false;
+    }
+
    adc_set_round_robin(_pinMask);
    adc_fifo_setup(true, true, 1, false, false);

@@ -196,7 +196,7 @@ static void extract_service(gatt_client_service_t * service, uint8_t * packet) {
    service->start_group_handle = little_endian_read_16(packet, 4);
    service->end_group_handle   = little_endian_read_16(packet, 6);
    service->uuid16 = 0;
-    reverse_128(&packet[8], service->uuid128);
+    reverse_128(&packet[12], service->uuid128);
    if (uuid_has_bluetooth_prefix(service->uuid128)) {
        service->uuid16 = big_endian_read_32(service->uuid128, 0);
    }
@@ -223,7 +223,7 @@ size_t A2DPSource::write(const uint8_t *buffer, size_t size) {
    size = std::min((size_t)availableForWrite(), size);

    size_t count = 0;
-    size /= 2;
+    size /= sizeof(int16_t); // Convert size to samples

    // First copy from writer to either end of
    uint32_t start = _pcmWriter;
@@ -262,7 +262,7 @@ int A2DPSource::availableForWrite() {
    } else {
        avail = _pcmBufferSize - _pcmWriter + _pcmReader - 1;
    }
-    avail /= sizeof(uint32_t); // availableForWrite always 32b sample pairs in this core...
+    avail *= sizeof(int16_t); // Convert samples to bytes
    return avail;
 }

@@ -125,6 +125,14 @@ public:
        return _hci.scan(mask, scanTimeSec, async);
    }

+    bool scanAsyncDone() {
+        return _hci.scanAsyncDone();
+    }
+
+    std::vector<BTDeviceInfo> scanAsyncResult() {
+        return _hci.scanAsyncResult();
+    }
+
    bool connect(const uint8_t *addr = nullptr);

    bool connected() {
@@ -151,6 +159,7 @@ public:
    }

    // from Print (see notes on write() methods below)
+    // Writes only full samples (size must be divisible by sample size in bytes)
    virtual size_t write(const uint8_t *buffer, size_t size) override;
    virtual int availableForWrite() override;

@@ -178,7 +178,7 @@ bool I2S::setLSBJFormat() {
 }

 bool I2S::setTDMFormat() {
-    if (_running || !_isOutput || _isInput) {
+    if (_running || !_isOutput) {
        return false;
    }
    _isTDM = true;
@@ -186,7 +186,7 @@ bool I2S::setTDMFormat() {
 }

 bool I2S::setTDMChannels(int channels) {
-    if (_running || !_isOutput || _isInput) {
+    if (_running || !_isOutput) {
        return false;
    }
    _tdmChannels = channels;
@@ -255,9 +255,9 @@ bool I2S::begin() {
    _isHolding = 0;
    int off = 0;
    if (!_swapClocks) {
-        _i2s = new PIOProgram(_isOutput ? (_isInput ? &pio_i2s_inout_program : (_isTDM ? &pio_tdm_out_program : (_isLSBJ ? &pio_lsbj_out_program : &pio_i2s_out_program))) : &pio_i2s_in_program);
+        _i2s = new PIOProgram(_isOutput ? (_isInput ? (_isTDM ? &pio_tdm_inout_program : &pio_i2s_inout_program) : (_isTDM ? &pio_tdm_out_program : (_isLSBJ ? &pio_lsbj_out_program : &pio_i2s_out_program))) : &pio_i2s_in_program);
    } else {
-        _i2s = new PIOProgram(_isOutput ? (_isInput ? &pio_i2s_inout_swap_program : (_isTDM ? &pio_tdm_out_swap_program : (_isLSBJ ? &pio_lsbj_out_swap_program : &pio_i2s_out_swap_program))) : &pio_i2s_in_swap_program);
+        _i2s = new PIOProgram(_isOutput ? (_isInput ? (_isTDM ? &pio_tdm_inout_swap_program : &pio_i2s_inout_swap_program) : (_isTDM ? &pio_tdm_out_swap_program : (_isLSBJ ? &pio_lsbj_out_swap_program : &pio_i2s_out_swap_program))) : &pio_i2s_in_swap_program);
    }
    int minpin, maxpin;
    if (_isOutput && _isInput) {
@@ -278,7 +278,11 @@ bool I2S::begin() {
    }
    if (_isOutput) {
        if (_isInput) {
-            pio_i2s_inout_program_init(_pio, _sm, off, _pinDIN, _pinDOUT, _pinBCLK, _bps, _swapClocks);
+            if (_isTDM) {
+                pio_tdm_inout_program_init(_pio, _sm, off, _pinDIN, _pinDOUT, _pinBCLK, _bps, _swapClocks, _tdmChannels);
+            } else {
+                pio_i2s_inout_program_init(_pio, _sm, off, _pinDIN, _pinDOUT, _pinBCLK, _bps, _swapClocks);
+            }
        } else if (_isTDM) {
            pio_tdm_out_program_init(_pio, _sm, off, _pinDOUT, _pinBCLK, _bps, _swapClocks, _tdmChannels);
        } else if (_isLSBJ) {
@@ -104,6 +104,41 @@ lastbit:
    ; Loop back to the beginning


+.program pio_tdm_inout
+.side_set 2   ; 0 = bclk, 1 = wclk
+; The C code should place (number of bits * channels - 1) in Y and update SHIFTCTRL
+; to be 32 (as per the TDM specs)
+;                           +----- WCLK
+;                           |+---- BCLK
+    mov x, y         side 0b01 [1]
+bitloop:
+    out pins, 1      side 0b00      ; Output changes on falling edge
+    in pins, 1       side 0b00      ; Sample input on falling edge
+    jmp x-- bitloop  side 0b11 [1]  ; Last bit toggles WCLK to mark frame boundary
+
+lastbit:
+    in pins, 1       side 0b10
+    out pins, 1      side 0b10
+    ; Loop back to the beginning
+
+
+.program pio_tdm_inout_swap
+.side_set 2   ; 0 = bclk, 1 = wclk
+; The C code should place (number of bits * channels - 1) in Y and update SHIFTCTRL
+; to be 32 (as per the TDM specs)
+;                           +----- WCLK
+;                           |+---- BCLK
+    mov x, y         side 0b10 [1]
+bitloop:
+    out pins, 1      side 0b00      ; Output changes on falling edge
+    in pins, 1       side 0b00      ; Sample input on falling edge
+    jmp x-- bitloop  side 0b11 [1]  ; Last bit toggles WCLK to mark frame boundary
+
+lastbit:
+    in pins, 1       side 0b01
+    out pins, 1      side 0b01
+    ; Loop back to the beginning
+

 .program pio_lsbj_out
 .side_set 2   ; 0 = bclk, 1=wclk
@@ -313,6 +348,42 @@ static inline void pio_tdm_out_program_init(PIO pio, uint sm, uint offset, uint
    pio_sm_exec(pio, sm, pio_encode_out(pio_osr, 32));
 }

+static inline void pio_tdm_inout_program_init(PIO pio, uint sm, uint offset, uint data_in_pin, uint data_out_pin, uint clock_pin_base, uint bits, bool swap, uint channels) {
+    pio_gpio_init(pio, data_in_pin);
+    pio_gpio_init(pio, data_out_pin);
+    pio_gpio_init(pio, clock_pin_base);
+    pio_gpio_init(pio, clock_pin_base + 1);
+
+    pio_sm_config c = swap ? pio_tdm_inout_swap_program_get_default_config(offset) : pio_tdm_inout_program_get_default_config(offset);
+
+    sm_config_set_in_pins(&c, data_in_pin);
+    sm_config_set_out_pins(&c, data_out_pin, 1);
+    sm_config_set_sideset_pins(&c, clock_pin_base);
+    sm_config_set_in_shift(&c, false, true, 32);
+    sm_config_set_out_shift(&c, false, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
+
+    pio_sm_init(pio, sm, offset, &c);
+
+    pio_sm_set_consecutive_pindirs(pio, sm, data_in_pin, 1, false);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_out_pin, 1, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, clock_pin_base, 2, true);
+    pio_sm_set_set_pins(pio, sm, data_out_pin, 1);
+    pio_sm_set_set_pins(pio, sm, clock_pin_base, 2);
+
+    // Initialize PIO state for TDM
+    // Can't set constant > 31, so push and pop/mov if needed
+    if (bits * channels - 1 > 31) {
+        pio_sm_put_blocking(pio, sm, bits * channels - 2);
+        pio_sm_exec(pio, sm, pio_encode_pull(false, false));
+        pio_sm_exec(pio, sm, pio_encode_mov(pio_y, pio_osr));
+    } else {
+        pio_sm_exec(pio, sm, pio_encode_set(pio_y, bits * channels - 2));
+    }
+
+    // Need to make OSR believe there's nothing left to shift out
+    pio_sm_exec(pio, sm, pio_encode_out(pio_osr, 32));
+}

 static inline void pio_lsbj_out_program_init(PIO pio, uint sm, uint offset, uint data_pin, uint clock_pin_base, uint bits, bool swap) {
    pio_gpio_init(pio, data_pin);
@@ -28,7 +28,7 @@ static const struct pio_program pio_i2s_mclk_program = {
    .instructions = pio_i2s_mclk_program_instructions,
    .length = 2,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_mclk_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -67,7 +67,7 @@ static const struct pio_program pio_i2s_out_program = {
    .instructions = pio_i2s_out_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_out_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -107,7 +107,7 @@ static const struct pio_program pio_i2s_out_swap_program = {
    .instructions = pio_i2s_out_swap_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_out_swap_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -143,7 +143,7 @@ static const struct pio_program pio_tdm_out_program = {
    .instructions = pio_tdm_out_program_instructions,
    .length = 4,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_tdm_out_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -179,7 +179,7 @@ static const struct pio_program pio_tdm_out_swap_program = {
    .instructions = pio_tdm_out_swap_program_instructions,
    .length = 4,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_tdm_out_swap_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -193,6 +193,82 @@ static inline pio_sm_config pio_tdm_out_swap_program_get_default_config(uint off
 }
 #endif

+// ------------- //
+// pio_tdm_inout //
+// ------------- //
+
+#define pio_tdm_inout_wrap_target 0
+#define pio_tdm_inout_wrap 5
+#define pio_tdm_inout_pio_version 0
+
+static const uint16_t pio_tdm_inout_program_instructions[] = {
+    //     .wrap_target
+    0xa922, //  0: mov    x, y            side 1 [1]
+    0x6001, //  1: out    pins, 1         side 0
+    0x4001, //  2: in     pins, 1         side 0
+    0x1941, //  3: jmp    x--, 1          side 3 [1]
+    0x5001, //  4: in     pins, 1         side 2
+    0x7001, //  5: out    pins, 1         side 2
+    //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program pio_tdm_inout_program = {
+    .instructions = pio_tdm_inout_program_instructions,
+    .length = 6,
+    .origin = -1,
+    .pio_version = pio_tdm_inout_pio_version,
+#if PICO_PIO_VERSION > 0
+    .used_gpio_ranges = 0x0
+#endif
+};
+
+static inline pio_sm_config pio_tdm_inout_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + pio_tdm_inout_wrap_target, offset + pio_tdm_inout_wrap);
+    sm_config_set_sideset(&c, 2, false, false);
+    return c;
+}
+#endif
+
+// ------------------ //
+// pio_tdm_inout_swap //
+// ------------------ //
+
+#define pio_tdm_inout_swap_wrap_target 0
+#define pio_tdm_inout_swap_wrap 5
+#define pio_tdm_inout_swap_pio_version 0
+
+static const uint16_t pio_tdm_inout_swap_program_instructions[] = {
+    //     .wrap_target
+    0xb122, //  0: mov    x, y            side 2 [1]
+    0x6001, //  1: out    pins, 1         side 0
+    0x4001, //  2: in     pins, 1         side 0
+    0x1941, //  3: jmp    x--, 1          side 3 [1]
+    0x4801, //  4: in     pins, 1         side 1
+    0x6801, //  5: out    pins, 1         side 1
+    //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program pio_tdm_inout_swap_program = {
+    .instructions = pio_tdm_inout_swap_program_instructions,
+    .length = 6,
+    .origin = -1,
+    .pio_version = pio_tdm_inout_swap_pio_version,
+#if PICO_PIO_VERSION > 0
+    .used_gpio_ranges = 0x0
+#endif
+};
+
+static inline pio_sm_config pio_tdm_inout_swap_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + pio_tdm_inout_swap_wrap_target, offset + pio_tdm_inout_swap_wrap);
+    sm_config_set_sideset(&c, 2, false, false);
+    return c;
+}
+#endif
+
 // ------------ //
 // pio_lsbj_out //
 // ------------ //
@@ -219,7 +295,7 @@ static const struct pio_program pio_lsbj_out_program = {
    .instructions = pio_lsbj_out_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_lsbj_out_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -259,7 +335,7 @@ static const struct pio_program pio_lsbj_out_swap_program = {
    .instructions = pio_lsbj_out_swap_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_lsbj_out_swap_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -299,7 +375,7 @@ static const struct pio_program pio_i2s_in_program = {
    .instructions = pio_i2s_in_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_in_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -339,7 +415,7 @@ static const struct pio_program pio_i2s_in_swap_program = {
    .instructions = pio_i2s_in_swap_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_in_swap_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -383,7 +459,7 @@ static const struct pio_program pio_i2s_inout_program = {
    .instructions = pio_i2s_inout_program_instructions,
    .length = 12,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_inout_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -427,7 +503,7 @@ static const struct pio_program pio_i2s_inout_swap_program = {
    .instructions = pio_i2s_inout_swap_program_instructions,
    .length = 12,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pio_i2s_inout_swap_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -490,6 +566,36 @@ static inline void pio_tdm_out_program_init(PIO pio, uint sm, uint offset, uint
    // Need to make OSR believe there's nothing left to shift out, or the 1st word will be the count we just passed in, not a sample
    pio_sm_exec(pio, sm, pio_encode_out(pio_osr, 32));
 }
+static inline void pio_tdm_inout_program_init(PIO pio, uint sm, uint offset, uint data_in_pin, uint data_out_pin, uint clock_pin_base, uint bits, bool swap, uint channels) {
+    pio_gpio_init(pio, data_in_pin);
+    pio_gpio_init(pio, data_out_pin);
+    pio_gpio_init(pio, clock_pin_base);
+    pio_gpio_init(pio, clock_pin_base + 1);
+    pio_sm_config c = swap ? pio_tdm_inout_swap_program_get_default_config(offset) : pio_tdm_inout_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, data_in_pin);
+    sm_config_set_out_pins(&c, data_out_pin, 1);
+    sm_config_set_sideset_pins(&c, clock_pin_base);
+    sm_config_set_in_shift(&c, false, true, 32);
+    sm_config_set_out_shift(&c, false, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_in_pin, 1, false);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_out_pin, 1, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, clock_pin_base, 2, true);
+    pio_sm_set_set_pins(pio, sm, data_out_pin, 1);
+    pio_sm_set_set_pins(pio, sm, clock_pin_base, 2);
+    // Initialize PIO state for TDM
+    // Can't set constant > 31, so push and pop/mov if needed
+    if (bits * channels - 1 > 31) {
+        pio_sm_put_blocking(pio, sm, bits * channels - 2);
+        pio_sm_exec(pio, sm, pio_encode_pull(false, false));
+        pio_sm_exec(pio, sm, pio_encode_mov(pio_y, pio_osr));
+    } else {
+        pio_sm_exec(pio, sm, pio_encode_set(pio_y, bits * channels - 2));
+    }
+    // Need to make OSR believe there's nothing left to shift out
+    pio_sm_exec(pio, sm, pio_encode_out(pio_osr, 32));
+}
 static inline void pio_lsbj_out_program_init(PIO pio, uint sm, uint offset, uint data_pin, uint clock_pin_base, uint bits, bool swap) {
    pio_gpio_init(pio, data_pin);
    pio_gpio_init(pio, clock_pin_base);
@@ -555,3 +661,4 @@ static inline void pio_i2s_inout_program_init(PIO pio, uint sm, uint offset, uin
 }

 #endif
+
@@ -31,7 +31,7 @@ static inline void pdm_pio_program_init(PIO pio, uint sm, uint offset, uint clkP
  pio_sm_set_consecutive_pindirs(pio, sm, dataPin, 1, false);
  pio_sm_set_consecutive_pindirs(pio, sm, clkPin, 1, true);
  pio_sm_set_pins_with_mask(pio, sm, 0, (1u << clkPin) );
-  //pio_gpio_init(pio, dataPin);
+  pio_gpio_init(pio, dataPin);
  pio_gpio_init(pio, clkPin);

  pio_sm_init(pio, sm, offset, &c);
@@ -28,7 +28,7 @@ static const struct pio_program pdm_pio_program = {
    .instructions = pdm_pio_program_instructions,
    .length = 2,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = pdm_pio_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -18,8 +18,8 @@ static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 16000, 1}, {11025, 116
 static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 16625, 1}, {11025, 24127, 2}, {16000, 16625, 2}, {22050, 24127, 4}, {32000, 16625, 4}, {44100, 24127, 8}, {48000, 16625, 6}, {88200, 24127, 16}, {96000, 16625, 12}, {176400, 47500, 63}, {192000, 16625, 24}};
 #elif F_CPU == 150000000
 static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 18750, 1}, {11025, 27211, 2}, {16000, 9375, 1}, {22050, 47619, 7}, {32000, 9375, 2}, {44100, 37415, 11}, {48000, 3125, 1}, {88200, 42517, 25}, {96000, 3125, 2}, {176400, 42517, 50}, {192000, 3125, 4}};
-#elif F_CPU == 175000000
-static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 21875, 1}, {11025, 15873, 1}, {16000, 21875, 2}, {22050, 15873, 2}, {32000, 21875, 4}, {44100, 15873, 4}, {48000, 21875, 6}, {88200, 15873, 8}, {96000, 21875, 12}, {176400, 62500, 63}, {192000, 21875, 24}};
+#elif F_CPU == 176000000
+static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 22000, 1}, {11025, 63855, 4}, {16000, 11000, 1}, {22050, 55873, 7}, {32000, 5500, 1}, {44100, 55873, 14}, {48000, 11000, 3}, {88200, 55873, 28}, {96000, 5500, 3}, {176400, 55873, 56}, {192000, 2750, 3}};
 #elif F_CPU == 200000000
 static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 25000, 1}, {11025, 54422, 3}, {16000, 12500, 1}, {22050, 63492, 7}, {32000, 6250, 1}, {44100, 31746, 7}, {48000, 12500, 3}, {88200, 15873, 7}, {96000, 6250, 3}, {176400, 53288, 47}, {192000, 3125, 3}};
 #elif F_CPU == 225000000
@@ -28,8 +28,8 @@ static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 28125, 1}, {11025, 204
 static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 30000, 1}, {11025, 65306, 3}, {16000, 15000, 1}, {22050, 32653, 3}, {32000, 7500, 1}, {44100, 59864, 11}, {48000, 5000, 1}, {88200, 62585, 23}, {96000, 2500, 1}, {176400, 62585, 46}, {192000, 1250, 1}};
 #elif F_CPU == 250000000
 static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 31250, 1}, {11025, 45351, 2}, {16000, 15625, 1}, {22050, 56689, 5}, {32000, 15625, 2}, {44100, 62358, 11}, {48000, 15625, 3}, {88200, 42517, 15}, {96000, 15625, 6}, {176400, 42517, 30}, {192000, 15625, 12}};
-#elif F_CPU == 275000000
-static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 34375, 1}, {11025, 49887, 2}, {16000, 34375, 2}, {22050, 37415, 3}, {32000, 34375, 4}, {44100, 37415, 6}, {48000, 34375, 6}, {88200, 37415, 12}, {96000, 34375, 12}, {176400, 35856, 23}, {192000, 34375, 24}};
+#elif F_CPU == 276000000
+static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 34500, 1}, {11025, 25034, 1}, {16000, 17250, 1}, {22050, 12517, 1}, {32000, 8625, 1}, {44100, 12517, 2}, {48000, 5750, 1}, {88200, 12517, 4}, {96000, 2875, 1}, {176400, 12517, 8}, {192000, 2875, 2}};
 #elif F_CPU == 300000000
 static const PWMPacerPrecalc __PWMAudio_pacer[] = {{8000, 37500, 1}, {11025, 27211, 1}, {16000, 18750, 1}, {22050, 27211, 2}, {32000, 9375, 1}, {44100, 47619, 7}, {48000, 6250, 1}, {88200, 37415, 11}, {96000, 3125, 1}, {176400, 42517, 25}, {192000, 3125, 2}};
 #else
@@ -263,8 +263,8 @@ void SPIClassRP2040::abortAsync() {


 bool SPIClassRP2040::setRX(pin_size_t pin) {
-#ifdef PICO_RP2350B
-    constexpr uint64_t valid[2] = { __bitset({0, 4, 16, 20, 32, 26}) /* SPI0 */,
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
+    constexpr uint64_t valid[2] = { __bitset({0, 4, 16, 20, 32, 36}) /* SPI0 */,
                                    __bitset({8, 12, 24, 28, 40, 44})  /* SPI1 */
                                  };
 #else
@@ -290,7 +290,7 @@ bool SPIClassRP2040::setRX(pin_size_t pin) {
 }

 bool SPIClassRP2040::setCS(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({1, 5, 17, 21, 33, 37}) /* SPI0 */,
                                    __bitset({9, 13, 25, 29, 41, 45})  /* SPI1 */
                                  };
@@ -317,7 +317,7 @@ bool SPIClassRP2040::setCS(pin_size_t pin) {
 }

 bool SPIClassRP2040::setSCK(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({2, 6, 18, 22, 34, 38}) /* SPI0 */,
                                    __bitset({10, 14, 26, 30, 42, 46})  /* SPI1 */
                                  };
@@ -344,7 +344,7 @@ bool SPIClassRP2040::setSCK(pin_size_t pin) {
 }

 bool SPIClassRP2040::setTX(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({3, 7, 19, 23, 35, 39}) /* SPI0 */,
                                    __bitset({11, 15, 27, 31, 43, 47})  /* SPI1 */
                                  };
@@ -25,65 +25,219 @@
 #include <hardware/spi.h>
 #include "SPIHelper.h"

+/**
+    @brief Implements a hardware-based SPI interface using the Pico's SPI blocks
+*/
 class SPIClassRP2040 : public arduino::HardwareSPI {
 public:
+    /**
+            @brief Create a PIO-based SPI instance, pins can be changed before begin() call
+
+            @param [in] spi SPI hardware instance (spi0/spi1)
+            @param [in] rx MISO GPIO
+            @param [in] cs CS GPIO
+            @param [in] sck SCK GPIO
+            @param [in] tx MOSI GPIO
+    */
    SPIClassRP2040(spi_inst_t *spi, pin_size_t rx, pin_size_t cs, pin_size_t sck, pin_size_t tx);

-    // Send or receive 8- or 16-bit data.  Returns read back value
+    /**
+           @brief Send an 8-bit byte of data and return read-back 8-bit value
+
+           @param [in] data Data to send
+           @returns Read back byte from SPI interface
+    */
    byte transfer(uint8_t data) override;
+
+    /**
+        @brief Send a 16-bit quantity over SPI and return read-back 16-bit value under a single CS assertion
+
+        @param [in] data Data to send
+        @returns Read back 16-bit quantity
+    */
    uint16_t transfer16(uint16_t data) override;

-    // Sends buffer in 8 bit chunks.  Overwrites buffer with read data
+
+    /**
+        @brief Sends buffer in 8 bit chunks under a single CS. Overwrites buffer with read data
+
+        @param [in, out] buf Buffer to read and write back into
+        @param [in] count Number of bytes to transmit/read
+    */
    void transfer(void *buf, size_t count) override;

-    // Sends one buffer and receives into another, much faster! can set rx or txbuf to nullptr
+    /**
+            @brief Sends one buffer and receives into another under a single CS. Can set rx or txbuf to nullptr
+
+            @param [in] txbuf Buffer to transmit or nullptr to send 0s
+            @param [out] rxbuf Buffer to read back into or nullptr to ignore returned data
+            @param [in] count Numbner of bytes to transmit/receive
+    */
    void transfer(const void *txbuf, void *rxbuf, size_t count) override;

    // DMA/asynchronous transfers.  Do not combime with synchronous runs or bad stuff will happen
    // All buffers must be valid for entire DMA and not touched until `finished()` returns true.
+    /**
+        @brief Perform a transfer() using DMA in the background. Returns immediately, need to check for completion
+
+        @details
+        Do not combine asynchronous and synchronous transfers.  All buffers must be valid until
+        the transfer reports that it is completed (``finished`` returns true).
+
+        @param [in] send Buffer to transmit, must remain valid through entire operation
+        @param [out] recv Buffer to receive, must remain valid through entire operation
+        @param [in] bytes Number of bytes to transfer under single CS
+    */
    bool transferAsync(const void *send, void *recv, size_t bytes);
-    bool finishedAsync(); // Call to check if the async operations is completed and the buffer can be reused/read
-    void abortAsync(); // Cancel an outstanding async operation
+    /**
+        @brief Call to check if the async operations is completed and the buffer can be reused/read
+
+        @returns True if the asynchronous SPI operation has completed and ``recv`` buffer is valid
+    */
+    bool finishedAsync();
+
+    /**
+        @brief Aborts an ongoing asynchronous SPI operation, if one is still operating
+
+        @details
+        Not normally needed, but in the case where a large, long SPI operation needs to be aborted
+        this call allows an application to safely stop the SPI and dispose of the ``recv`` and
+        ``send`` buffers
+    */
+    void abortAsync();


-    // Call before/after every complete transaction
+    /**
+           @brief Begin an SPI transaction, sets SPI speed and masks necessary interrupts
+
+           @param [in] SPISettings SPI configuration parameters, including the clock speed
+    */
    void beginTransaction(SPISettings settings) override;
+
+    /**
+            @brief Ends an SPI transaction, unmasks and masked GPIO interrupts
+    */
    void endTransaction(void) override;

-    // Assign pins, call before begin()
+    /**
+           @brief Sets the MISO(RX) pin. Call before begin()
+
+           @param [in] pin The GPIO number to assign to
+           @returns True on success
+    */
    bool setRX(pin_size_t pin);
+
+    /**
+            @brief Sets the MISO(RX) pin. Call before begin()
+
+            @param [in] pin The GPIO number to assign to
+            @returns True on success
+    */
    inline bool setMISO(pin_size_t pin) {
        return setRX(pin);
    }
+
+    /**
+            @brief Sets the CS pin. Call before begin()
+
+            @param [in] pin The GPIO number to assign to
+            @returns True on success
+    */
    bool setCS(pin_size_t pin);
+
+    /**
+            @brief Sets the SCK pin. Call before begin()
+
+            @param [in] pin The GPIO number to assign to
+            @returns True on success
+    */
    bool setSCK(pin_size_t pin);
+
+    /**
+          @brief Sets the MOSI(TX) pin. Call before begin()
+
+          @param [in] pin The GPIO number to assign to
+          @returns True on success
+    */
    bool setTX(pin_size_t pin);
+
+    /**
+          @brief Sets the MOSI(TX) pin. Call before begin()
+
+          @param [in] pin The GPIO number to assign to
+          @returns True on success
+    */
    inline bool setMOSI(pin_size_t pin) {
        return setTX(pin);
    }

-    // Call once to init/deinit SPI class, select pins, etc.
+    /**
+            @brief Call once to init/deinit SPI class, select pins, etc.
+    */
    virtual void begin() override {
        begin(false);
    }
+
+    /**
+           @brief Call once to init/deinit SPI class, select pins, etc.
+
+           @param [in] hwCS Pass in true to enable HW-controlled CS.  Otherwise application needs to assert/deassert CS.
+    */
    void begin(bool hwCS);
+
+    /**
+           @brief Call to deinit and disable the SPI interface.
+    */
    void end() override;

-    // Deprecated - do not use!
+    /**
+            @brief Deprecated, do not use
+
+            @param [in] order Deprecated
+    */
    void setBitOrder(BitOrder order) __attribute__((deprecated));
+
+    /**
+            @brief Deprecated, do not use
+
+            @param [in] order Deprecated
+    */
    void setDataMode(uint8_t uc_mode) __attribute__((deprecated));
+
+    /**
+            @brief Deprecated, do not use
+
+            @param [in] order Deprecated
+    */
    void setClockDivider(uint8_t uc_div) __attribute__((deprecated));

-    // List of GPIO IRQs to disable during a transaction
+    /**
+            @brief Ensure specific GPIO interrupt is disabled during and SPI transaction to protect against re-entrancy.  Multiple GPIOs supported by multiple calls.
+
+            @param [in] interruptNumber GPIO pin to mask
+    */
    virtual void usingInterrupt(int interruptNumber) override {
        _helper.usingInterrupt(interruptNumber);
    }

+    /**
+            @brief Remove a GPIO from the masked-during-transaction list.
+
+            @param [in] interruptNumber GPIO pin to unmask
+    */
    virtual void notUsingInterrupt(int interruptNumber) override {
        _helper.notUsingInterrupt(interruptNumber);
    }
-    virtual void attachInterrupt() override { /* noop */ }
-    virtual void detachInterrupt() override { /* noop */ }
+
+    /**
+           @brief Deprecated, do not use
+    */
+    virtual void attachInterrupt() override  __attribute__((deprecated)) { /* noop */ }
+
+    /**
+           @brief Deprecated, do not use
+    */
+    virtual void detachInterrupt() override  __attribute__((deprecated)) { /* noop */ }

 private:
    void adjustBuffer(const void *s, void *d, size_t cnt, bool by16);
@@ -98,7 +98,7 @@ public:
        return (reverseByte(w & 0xff) << 8) | (reverseByte(w >> 8));
    }

-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    static constexpr int GPIOIRQREGS = 6;
 #else
    static constexpr int GPIOIRQREGS = 4;
@@ -108,6 +108,9 @@ public:
        @brief Disables any GPIO interrupts registered before an SPI transaction begins
    */
    void maskInterrupts() {
+        if (_usingIRQs.empty()) {
+            return;
+        }
        noInterrupts(); // Avoid possible race conditions if IRQ comes in while main app is in middle of this
        // Disable any IRQs that are being used for SPI
        io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
@@ -134,6 +137,9 @@ public:
        @brief Restores GPIO interrupts masks after an SPI transaction completes
    */
    void unmaskInterrupts() {
+        if (_usingIRQs.empty()) {
+            return;
+        }
        noInterrupts(); // Avoid race condition so the GPIO IRQs won't come back until all state is restored
        DEBUGSPI("SPI::endTransaction()\n");
        // Re-enable IRQs
@@ -79,7 +79,7 @@ inline spi_cpha_t SPISlaveClass::cpha(SPISettings _spis) {
 }

 bool SPISlaveClass::setRX(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({0, 4, 16, 20, 32, 26}) /* SPI0 */,
                                    __bitset({8, 12, 24, 28, 40, 44})  /* SPI1 */
                                  };
@@ -106,7 +106,7 @@ bool SPISlaveClass::setRX(pin_size_t pin) {
 }

 bool SPISlaveClass::setCS(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({1, 5, 17, 21, 33, 37}) /* SPI0 */,
                                    __bitset({9, 13, 25, 29, 41, 45})  /* SPI1 */
                                  };
@@ -133,7 +133,7 @@ bool SPISlaveClass::setCS(pin_size_t pin) {
 }

 bool SPISlaveClass::setSCK(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({2, 6, 18, 22, 34, 38}) /* SPI0 */,
                                    __bitset({10, 14, 26, 30, 42, 46})  /* SPI1 */
                                  };
@@ -160,7 +160,7 @@ bool SPISlaveClass::setSCK(pin_size_t pin) {
 }

 bool SPISlaveClass::setTX(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({3, 7, 19, 23, 35, 39}) /* SPI0 */,
                                    __bitset({11, 15, 27, 31, 43, 47})  /* SPI1 */
                                  };
@@ -36,7 +36,7 @@ static const struct pio_program servo_program = {
    .instructions = servo_program_instructions,
    .length = 8,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = servo_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -25,6 +25,9 @@
 #include <api/HardwareSPI.h>
 #include <hardware/spi.h>

+/**
+    @brief Implements a PIO-based SPI interface without pin restrictions
+*/
 class SoftwareSPI : public arduino::HardwareSPI {
 public:
    /**
@@ -37,53 +40,170 @@ public:
    */
    SoftwareSPI(pin_size_t sck, pin_size_t miso, pin_size_t mosi, pin_size_t cs = -1);

-    // Send or receive 8- or 16-bit data.  Returns read back value
+    /**
+        @brief Send an 8-bit byte of data and return read-back 8-bit value
+
+        @param [in] data Data to send
+        @returns Read back byte from SPI interface
+    */
    byte transfer(uint8_t data) override;
+
+    /**
+        @brief Send a 16-bit quantity over SPI and return read-back 16-bit value under a single CS assertion
+
+        @param [in] data Data to send
+        @returns Read back 16-bit quantity
+    */
    uint16_t transfer16(uint16_t data) override;

-    // Sends buffer in 8 bit chunks.  Overwrites buffer with read data
+    /**
+        @brief Sends buffer in 8 bit chunks under a single CS. Overwrites buffer with read data
+
+        @param [in, out] buf Buffer to read and write back into
+        @param [in] count Number of bytes to transmit/read
+    */
    void transfer(void *buf, size_t count) override;

-    // Sends one buffer and receives into another, much faster! can set rx or txbuf to nullptr
+    /**
+        @brief Sends one buffer and receives into another under a single CS. Can set rx or txbuf to nullptr
+
+        @param [in] txbuf Buffer to transmit or nullptr to send 0s
+        @param [out] rxbuf Buffer to read back into or nullptr to ignore returned data
+        @param [in] count Numbner of bytes to transmit/receive
+    */
    void transfer(const void *txbuf, void *rxbuf, size_t count) override;

-    // Call before/after every complete transaction
+    /**
+        @brief Begin an SPI transaction, sets SPI speed and masks necessary interrupts
+
+        @param [in] SPISettings SPI configuration parameters, including the clock speed
+    */
    void beginTransaction(SPISettings settings) override;
+
+    /**
+        @brief Ends an SPI transaction, unmasks and masked GPIO interrupts
+    */
    void endTransaction(void) override;

-    // Assign pins, call before begin()
+    /**
+        @brief Sets the MISO(RX) pin. Call before begin()
+
+        @param [in] pin The GPIO number to assign to
+        @returns True on success
+    */
    bool setMISO(pin_size_t pin);
+
+    /**
+        @brief Sets the MISO(RX) pin. Call before begin()
+
+        @param [in] pin The GPIO number to assign to
+        @returns True on success
+    */
    inline bool setRX(pin_size_t pin) {
        return setMISO(pin);
    }
+
+    /**
+        @brief Sets the CS pin. Call before begin()
+
+        @param [in] pin The GPIO number to assign to
+        @returns True on success
+    */
    bool setCS(pin_size_t pin);
+
+    /**
+        @brief Sets the SCK pin. Call before begin()
+
+        @param [in] pin The GPIO number to assign to
+        @returns True on success
+    */
    bool setSCK(pin_size_t pin);
+
+    /**
+        @brief Sets the MOSI(TX) pin. Call before begin()
+
+        @param [in] pin The GPIO number to assign to
+        @returns True on success
+    */
    bool setMOSI(pin_size_t pin);
+
+    /**
+        @brief Sets the MOSI(TX) pin. Call before begin()
+
+        @param [in] pin The GPIO number to assign to
+        @returns True on success
+    */
    inline bool setTX(pin_size_t pin) {
        return setMOSI(pin);
    }

-    // Call once to init/deinit SPI class, select pins, etc.
+    /**
+        @brief Call once to init/deinit SPI class, select pins, etc.
+    */
    virtual void begin() override {
        begin(false);
    }
+
+    /**
+        @brief Call once to init/deinit SPI class, select pins, etc.
+
+        @param [in] hwCS Pass in true to enable HW-controlled CS.  Otherwise application needs to assert/deassert CS.
+    */
    void begin(bool hwCS);
+
+    /**
+        @brief Call to deinit and disable the SPI interface.
+    */
    void end() override;

-    // Deprecated - do not use!
+    /**
+        @brief Deprecated, do not use
+
+        @param [in] order Deprecated
+    */
    void setBitOrder(BitOrder order) __attribute__((deprecated));
+
+    /**
+        @brief Deprecated, do not use
+
+        @param [in] uc_mode Deprecated
+    */
    void setDataMode(uint8_t uc_mode) __attribute__((deprecated));
+
+    /**
+        @brief Deprecated, do not use
+
+        @param [in] uc_div Deprecated
+    */
    void setClockDivider(uint8_t uc_div) __attribute__((deprecated));

-    // List of GPIO IRQs to disable during a transaction
+    /**
+        @brief Ensure specific GPIO interrupt is disabled during and SPI transaction to protect against re-entrancy.  Multiple GPIOs supported by multiple calls.
+
+        @param [in] interruptNumber GPIO pin to mask
+    */
    virtual void usingInterrupt(int interruptNumber) override {
        _helper.usingInterrupt(interruptNumber);
    }
+
+    /**
+        @brief Remove a GPIO from the masked-during-transaction list.
+
+        @param [in] interruptNumber GPIO pin to unmask
+    */
    virtual void notUsingInterrupt(int interruptNumber) override {
        _helper.notUsingInterrupt(interruptNumber);
    }
-    virtual void attachInterrupt() override { /* noop */ }
-    virtual void detachInterrupt() override { /* noop */ }
+
+    /**
+        @brief Deprecated, do not use
+    */
+    virtual void attachInterrupt() override __attribute__((deprecated)) { /* noop */ }
+
+    /**
+        @brief Deprecated, do not use
+    */
+    virtual void detachInterrupt() override __attribute__((deprecated)) { /* noop */ }

 private:
    void _adjustPIO(int bits);
@@ -28,7 +28,7 @@ static const struct pio_program spi_cpha0_program = {
    .instructions = spi_cpha0_program_instructions,
    .length = 2,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = spi_cpha0_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -63,7 +63,7 @@ static const struct pio_program spi_cpha1_program = {
    .instructions = spi_cpha1_program_instructions,
    .length = 3,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = spi_cpha1_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -133,7 +133,7 @@ static const struct pio_program spi_cpha0_cs_program = {
    .instructions = spi_cpha0_cs_program_instructions,
    .length = 9,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = spi_cpha0_cs_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -176,7 +176,7 @@ static const struct pio_program spi_cpha1_cs_program = {
    .instructions = spi_cpha1_cs_program_instructions,
    .length = 9,
    .origin = -1,
-    .pio_version = 0,
+    .pio_version = spi_cpha1_cs_pio_version,
 #if PICO_PIO_VERSION > 0
    .used_gpio_ranges = 0x0
 #endif
@@ -35,8 +35,8 @@
 #if USE_WIFI
 #include <WiFi.h>
 #elif USE_WIRED
-#include <W5500lwIP.h> // Or W5100lwIP.h or ENC28J60lwIP.h
-Wiznet5500lwIP eth(1 /* chip select */); // or Wiznet5100lwIP or ENC28J60lwIP
+#include <W5500lwIP.h> // or W6100lwIP.h or W5100lwIP.h or ENC28J60lwIP.h
+Wiznet5500lwIP eth(1 /* SPI chip select */); // or Wiznet6100lwIP or Wiznet5100lwIP or ENC28J60lwIP
 #endif

 #include <WiFiClient.h>
@@ -6,42 +6,53 @@
 const char* ssl_host = "www.akamai.com";
 const uint16_t ssl_port = 443;

+// openssl s_client -connect www.akamai.com:443  < /dev/null 2>/dev/null | openssl x509 -fingerprint -noout -in /dev/stdin | cut -f2 -d= | sed 's/^/const char fingerprint_ssl[] = "/' | sed 's/$/";/'
+const char fingerprint_ssl[] = "D6:6C:EF:1A:8A:CE:27:18:D4:0C:83:2C:AE:4D:1B:B9:4C:B8:C9:83";

-const char fingerprint_ssl [] PROGMEM = "48:EF:70:29:41:CE:64:C9:DF:57:A2:46:E8:34:E1:50:0B:70:AE:17";
-const char pubkey_ssl [] PROGMEM = R"PUBKEY(
+// openssl s_client -connect www.akamai.com:443 < /dev/null 2>/dev/null | openssl x509 -pubkey -noout
+const char pubkey_ssl[] = R"PUBKEY(
 -----BEGIN PUBLIC KEY-----
-MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEiuc+zlu43bv55+s0Fj6RiBW+olZm
-c/AkoTP48CFCIGP1DET7Oufx6oe63GIuBzdVfR5D6R2z818b5gY1o2lBxg==
+MFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAE2BD04+A9idhYCHJ4RBy2KHtvJAsz
+KLkAzZOWDEqjNu4plNmiWMymBw0rJggZOU4/TE+a4KqzBgsus9QkFZh88w==
 -----END PUBLIC KEY-----
 )PUBKEY";

-const char cert_CA [] PROGMEM = R"CERT(
+// openssl s_client -connect www.akamai.com:443 < /dev/null 2> /dev/null | openssl x509
+
+const char cert_CA[]  = R"CERT(
 -----BEGIN CERTIFICATE-----
-MIIEvjCCA6agAwIBAgIQBtjZBNVYQ0b2ii+nVCJ+xDANBgkqhkiG9w0BAQsFADBh
-MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3
-d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD
-QTAeFw0yMTA0MTQwMDAwMDBaFw0zMTA0MTMyMzU5NTlaME8xCzAJBgNVBAYTAlVT
-MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxKTAnBgNVBAMTIERpZ2lDZXJ0IFRMUyBS
-U0EgU0hBMjU2IDIwMjAgQ0ExMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKC
-AQEAwUuzZUdwvN1PWNvsnO3DZuUfMRNUrUpmRh8sCuxkB+Uu3Ny5CiDt3+PE0J6a
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-Afr5yjK7tI4nhyfFK3TUqNaX3sNk+crOU6JWvHgXjkkDKa77SU+kFbnO8lwZV21r
-eacroicgE7XQPUDTITAHk+qZ9QIDAQABo4IBgjCCAX4wEgYDVR0TAQH/BAgwBgEB
-/wIBADAdBgNVHQ4EFgQUt2ui6qiqhIx56rTaD5iyxZV2ufQwHwYDVR0jBBgwFoAU
-A95QNVbRTLtm8KPiGxvDl7I90VUwDgYDVR0PAQH/BAQDAgGGMB0GA1UdJQQWMBQG
-CCsGAQUFBwMBBggrBgEFBQcDAjB2BggrBgEFBQcBAQRqMGgwJAYIKwYBBQUHMAGG
-GGh0dHA6Ly9vY3NwLmRpZ2ljZXJ0LmNvbTBABggrBgEFBQcwAoY0aHR0cDovL2Nh
-Y2VydHMuZGlnaWNlcnQuY29tL0RpZ2lDZXJ0R2xvYmFsUm9vdENBLmNydDBCBgNV
-HR8EOzA5MDegNaAzhjFodHRwOi8vY3JsMy5kaWdpY2VydC5jb20vRGlnaUNlcnRH
-bG9iYWxSb290Q0EuY3JsMD0GA1UdIAQ2MDQwCwYJYIZIAYb9bAIBMAcGBWeBDAEB
-MAgGBmeBDAECATAIBgZngQwBAgIwCAYGZ4EMAQIDMA0GCSqGSIb3DQEBCwUAA4IB
-AQCAMs5eC91uWg0Kr+HWhMvAjvqFcO3aXbMM9yt1QP6FCvrzMXi3cEsaiVi6gL3z
-ax3pfs8LulicWdSQ0/1s/dCYbbdxglvPbQtaCdB73sRD2Cqk3p5BJl+7j5nL3a7h
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-A7sKPPcw7+uvTPyLNhBzPvOk
+MIIGAzCCBOugAwIBAgIQA0bb8BLx/7BiUlnlhKlA6TANBgkqhkiG9w0BAQsFADBP
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+bTA+BgNVHSAENzA1MDMGBmeBDAECAjApMCcGCCsGAQUFBwIBFhtodHRwOi8vd3d3
+LmRpZ2ljZXJ0LmNvbS9DUFMwDgYDVR0PAQH/BAQDAgOIMB0GA1UdJQQWMBQGCCsG
+AQUFBwMBBggrBgEFBQcDAjCBjwYDVR0fBIGHMIGEMECgPqA8hjpodHRwOi8vY3Js
+My5kaWdpY2VydC5jb20vRGlnaUNlcnRUTFNSU0FTSEEyNTYyMDIwQ0ExLTQuY3Js
+MECgPqA8hjpodHRwOi8vY3JsNC5kaWdpY2VydC5jb20vRGlnaUNlcnRUTFNSU0FT
+SEEyNTYyMDIwQ0ExLTQuY3JsMH8GCCsGAQUFBwEBBHMwcTAkBggrBgEFBQcwAYYY
+aHR0cDovL29jc3AuZGlnaWNlcnQuY29tMEkGCCsGAQUFBzAChj1odHRwOi8vY2Fj
+ZXJ0cy5kaWdpY2VydC5jb20vRGlnaUNlcnRUTFNSU0FTSEEyNTYyMDIwQ0ExLTEu
+Y3J0MAwGA1UdEwEB/wQCMAAwggF+BgorBgEEAdZ5AgQCBIIBbgSCAWoBaAB2ABLx
+TjS9U3JMhAYZw48/ehP457Vih4icbTAFhOvlhiY6AAABkbhvAhwAAAQDAEcwRQIh
+AKw2mqyB5bKpwGN5Dn4rLL5pjsNY03bEnNpVXltFpOtDAiBmwhRQg/V+whwdynkK
+OOyuChdAd2JH76KE+XISMjPM3gB1AObSMWNAd4zBEEEG13G5zsHSQPaWhIb7uocy
+Hf0eN45QAAABkbhvAm8AAAQDAEYwRAIgOw/ZyiiIsgDbM55pvJmV/CvwA5AGWbpC
+lB9q78TiJj4CIC2d9w9Ntb3HTOrLQvwSiNOrpop+deZ3fa1LQ92miaclAHcAzPsP
+aoVxCWX+lZtTzumyfCLphVwNl422qX5UwP5MDbAAAAGRuG8CMAAABAMASDBGAiEA
+oSSK9/26Uk3fqp7btK2SaEyWM/u++sOZXMeEOefnKwUCIQCqKysJztOF58PueXeE
+pLliBWZUnjUrvPIbtxp31gQQITANBgkqhkiG9w0BAQsFAAOCAQEAAoJryZtJc8oc
+hf5vflkW2w0PdJ5NpbmjZOMTyutBRaJpxrDqKnjKBEOp6liZ2pDbUngGAwLEM30
+KRBwJCc44u7w8Kj/KOoIZFoh9SiONAEn1qXWF0nFkYAD8J8yYwzkJy7fa3sdodaI
+ex5NJosK/tyXjEBOcTrBsXkzs55pjSi+KJiiOHs/hDuBdyDtJs1ENAOswd8AWMSk
+S9WycNxxEFH9VQgwgUhaI5Lc9J8rt3IJur1wp1JoDwdjIhs1M0rofgdW716UpmQ9
+visdfGu8fCAlDSBPPC6gUPlFGFf4ujUmprJyBQ5xsYva0sVqhGbaoxtV7FdMDJkg
+nDRma+9lPA==
 -----END CERTIFICATE-----
 )CERT";
@@ -19,6 +19,8 @@
    You should have received a copy of the GNU Lesser General Public
    License along with this library; if not, write to the Free Software
    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+    Modified May 2025 by Sven Bruns (Lorandil on GitHub) to support user defined buffer size (inspired by ESP32 code)
 */

 #include <Arduino.h>
@@ -46,10 +48,14 @@ TwoWire::TwoWire(i2c_inst_t *i2c, pin_size_t sda, pin_size_t scl) {
    _running = false;
    _txBegun = false;
    _buffLen = 0;
+
+    // allocate buffer memory early, so we don't fragment the heap later
+    _buffSize = WIRE_BUFFER_SIZE;
+    _buff = (uint8_t *)malloc(_buffSize);
 }

 bool TwoWire::setSDA(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44}) /* I2C0 */,
                                    __bitset({2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46})  /* I2C1 */
                                  };
@@ -76,7 +82,7 @@ bool TwoWire::setSDA(pin_size_t pin) {
 }

 bool TwoWire::setSCL(pin_size_t pin) {
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
    constexpr uint64_t valid[2] = { __bitset({1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45}) /* I2C0 */,
                                    __bitset({3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47})  /* I2C1 */
                                  };
@@ -158,6 +164,16 @@ void TwoWire::begin(uint8_t addr) {
        // ERROR
        return;
    }
+
+    // allocate buffer if necessary
+    if (!_buff) {
+        _buff = (uint8_t *)malloc(_buffSize);
+        if (!_buff) {
+            // ERROR
+            return;
+        }
+    }
+
    _slave = true;
    i2c_init(_i2c, _clkHz);
    i2c_set_slave_mode(_i2c, true, addr);
@@ -192,7 +208,7 @@ void TwoWire::onIRQ() {
    // First, pull off any data available
    if (irqstat & (1 << 2)) {
        // RX_FULL
-        if (_buffLen < (int)sizeof(_buff)) {
+        if (_buffLen < int(_buffSize)) {
            _buff[_buffLen++] = _i2c->hw->data_cmd & 0xff;
        } else {
            _i2c->hw->data_cmd;
@@ -271,7 +287,7 @@ void TwoWire::beginTransmission(uint8_t addr) {
 }

 size_t TwoWire::requestFrom(uint8_t address, size_t quantity, bool stopBit) {
-    if (!_running || _txBegun || !quantity || (quantity > sizeof(_buff))) {
+    if (!_running || _txBegun || !quantity || (quantity > _buffSize)) {
        return 0;
    }

@@ -448,7 +464,7 @@ size_t TwoWire::write(uint8_t ucData) {
            return 0;
        }
    } else {
-        if (!_txBegun || (_buffLen == sizeof(_buff))) {
+        if (!_txBegun || (_buffLen == int(_buffSize))) {
            return 0;
        }
        _buff[_buffLen++] = ucData;
@@ -745,6 +761,20 @@ void TwoWire::clearTimeoutFlag() {
    _timeoutFlag = false;
 }

+size_t TwoWire::setBufferSize(size_t bSize) {
+    if (_running) {
+        // ERROR - transmission already running. Report back current buffer size
+        return _buffSize;
+    }
+    // only free the buffer, if it already exists and the new size differs from the current one
+    if (_buff && (bSize != _buffSize)) {
+        free(_buff);
+        _buff = nullptr;
+    }
+    _buffSize = max(WIRE_BUFFER_SIZE_MIN, int(bSize)); // enforce minimum buffer size
+    return _buffSize;
+}
+
 #ifndef __WIRE0_DEVICE
 #define __WIRE0_DEVICE i2c0
 #endif
@@ -19,6 +19,8 @@
    You should have received a copy of the GNU Lesser General Public
    License along with this library; if not, write to the Free Software
    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+    Modified May 2025 by Sven Bruns (Lorandil on GitHub) to support user defined buffer size (inspired by ESP32 code)
 */

 #pragma once
@@ -30,8 +32,14 @@
 // WIRE_HAS_END means Wire has end()
 #define WIRE_HAS_END 1

+// WIRE_HAS_BUFFER_SIZE means Wire has setBufferSize()
+#define WIRE_HAS_BUFFER_SIZE 1
+
 #ifndef WIRE_BUFFER_SIZE
-#define WIRE_BUFFER_SIZE 256
+#define WIRE_BUFFER_SIZE 256    // default size, if none is set using Wire::setBuffersize(size_t)
+#endif
+#ifndef WIRE_BUFFER_SIZE_MIN
+#define WIRE_BUFFER_SIZE_MIN 32 // minimum size for safe operation
 #endif

 class TwoWire : public HardwareI2C {
@@ -97,6 +105,8 @@ public:
    bool getTimeoutFlag(void);
    void clearTimeoutFlag(void);

+    size_t setBufferSize(size_t bSize);	// set buffer size (call prior to 'begin()')
+
    // IRQ callback
    void onIRQ();

@@ -115,7 +125,9 @@ private:
    bool _reset_with_timeout;
    void _handleTimeout(bool reset);

-    uint8_t _buff[WIRE_BUFFER_SIZE];
+    uint8_t *_buff;         // pointer to i2c buffer
+    size_t  _buffSize;      // current buffer size
+
    int _buffLen;
    int _buffOff;

@@ -75,7 +75,7 @@ void __removeEthernetPacketHandler(int id) {
 }

 #define GPIOSTACKSIZE 8
-#ifdef PICO_RP2350B
+#if defined(PICO_RP2350) && !PICO_RP2350A // RP2350B
 #define GPIOIRQREGS 6
 #define GPIOIRQREGSINIT 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
 #else
@@ -186,6 +186,7 @@ protected:
    SPIClass& _spiUnit;
    SPISettings _spiSettings = SPISettings(4000000, MSBFIRST, SPI_MODE0);
    netif _netif;
+    bool _isDHCP = true;

    uint16_t _mtu;
    int8_t   _intrPin;
@@ -282,6 +283,8 @@ bool LwipIntfDev<RawDev>::config(const IPAddress& localIP, const IPAddress& gate
        return false;
    }

+    _isDHCP = (localIP.v4() == 0);
+
    IPAddress realGateway, realNetmask, realDns1;
    if (!ipAddressReorder(localIP, gateway, netmask, dns1, realGateway, realNetmask, realDns1)) {
        return false;
@@ -389,8 +392,11 @@ bool LwipIntfDev<RawDev>::begin(const uint8_t* macAddress, const uint16_t mtu) {
        _phID = __addEthernetPacketHandler([this] { this->handlePackets(); });
    }

-    if (localIP().v4() == 0) {
-        // IP not set, starting DHCP
+    if (_isDHCP) {
+        // Destroy any existing address
+        ip4_addr_set_u32(ip_2_ip4(&_netif.ip_addr), 0);
+
+        // Start a new DHCP request
        _netif.flags |= NETIF_FLAG_UP;
        switch (dhcp_start(&_netif)) {
        case ERR_OK:
@@ -8,7 +8,7 @@
 const char* host = "djxmmx.net";
 const uint16_t port = 17;

-Wiznet55rp20lwIP eth(1 /* chip select */);
+Wiznet55rp20lwIP eth(20 /* chip select */);

 void setup() {
  Serial.begin(115200);
@@ -51,7 +51,7 @@ public:
        Constructor that uses the default hardware SPI pins
        @param cs the Arduino Chip Select / Slave Select pin (default 10)
    */
-    Wiznet55rp20(int8_t cs = SS, SPIClass& spi = SPI, int8_t intr = -1);
+    Wiznet55rp20(int8_t cs = WIZNET_PIO_SPI_CS_PIN, SPIClass& spi = SPI, int8_t intr = -1);
    //Wiznet55rp20();

    /**
@@ -14,6 +14,7 @@

 #define wiznet_pio_spi_write_read_wrap_target 0
 #define wiznet_pio_spi_write_read_wrap 8
+#define wiznet_pio_spi_write_read_pio_version 0

 #define wiznet_pio_spi_write_read_offset_write_bits 0u
 #define wiznet_pio_spi_write_read_offset_write_end 3u
@@ -38,6 +39,10 @@ static const struct pio_program wiznet_pio_spi_write_read_program = {
    .instructions = wiznet_pio_spi_write_read_program_instructions,
    .length = 9,
    .origin = -1,
+    .pio_version = wiznet_pio_spi_write_read_pio_version,
+#if PICO_PIO_VERSION > 0
+    .used_gpio_ranges = 0x0
+#endif
 };

 static inline pio_sm_config wiznet_pio_spi_write_read_program_get_default_config(uint offset) {
@@ -0,0 +1,95 @@
+/*
+    This sketch establishes a TCP connection to a "quote of the day" service.
+    It sends a "hello" message, and then prints received data.
+*/
+
+#include <W6300lwIP.h>
+
+const char* host = "djxmmx.net";
+const uint16_t port = 17;
+
+Wiznet6300lwIP eth(1 /* chip select */);
+
+void setup() {
+  // Set up SPI pinout to match your HW
+  SPI.setRX(0);
+  SPI.setCS(1);
+  SPI.setSCK(2);
+  SPI.setTX(3);
+
+  Serial.begin(115200);
+  delay(5000);
+  Serial.println();
+  Serial.println();
+  Serial.println("Starting Ethernet port");
+
+  // Start the Ethernet port
+  if (!eth.begin()) {
+    Serial.println("No wired Ethernet hardware detected. Check pinouts, wiring.");
+    while (1) {
+      delay(1000);
+    }
+  }
+
+  while (!eth.connected()) {
+    Serial.print(".");
+    delay(500);
+  }
+
+  Serial.println("");
+  Serial.println("Ethernet connected");
+  Serial.println("IP address: ");
+  Serial.println(eth.localIP());
+}
+
+void loop() {
+  static bool wait = false;
+
+  Serial.print("connecting to ");
+  Serial.print(host);
+  Serial.print(':');
+  Serial.println(port);
+
+  // Use WiFiClient class to create TCP connections
+  WiFiClient client;
+  if (!client.connect(host, port)) {
+    Serial.println("connection failed");
+    delay(5000);
+    return;
+  }
+
+  // This will send a string to the server
+  Serial.println("sending data to server");
+  if (client.connected()) {
+    client.println("hello from RP2040");
+  }
+
+  // wait for data to be available
+  unsigned long timeout = millis();
+  while (client.available() == 0) {
+    if (millis() - timeout > 5000) {
+      Serial.println(">>> Client Timeout !");
+      client.stop();
+      delay(60000);
+      return;
+    }
+  }
+
+  // Read all the lines of the reply from server and print them to Serial
+  Serial.println("receiving from remote server");
+  // not testing 'client.connected()' since we do not need to send data here
+  while (client.available()) {
+    char ch = static_cast<char>(client.read());
+    Serial.print(ch);
+  }
+
+  // Close the connection
+  Serial.println();
+  Serial.println("closing connection");
+  client.stop();
+
+  if (wait) {
+    delay(300000);  // execute once every 5 minutes, don't flood remote service
+  }
+  wait = true;
+}
@@ -0,0 +1,18 @@
+#######################################
+# Syntax Coloring Map
+#######################################
+
+#######################################
+# Library (KEYWORD1)
+#######################################
+
+W6100lwIP	KEYWORD1
+Wiznet6100lwIP	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+#######################################
+# Constants (LITERAL1)
+#######################################
@@ -0,0 +1,10 @@
+name=lwIP_w6300
+version=1
+author=Stefan Nuernberger
+maintainer=esp8266/Arduino
+sentence=Ethernet driver
+paragraph=Wiznet6300 ethernet drivers for lwIP and esp8266 Arduino from https://github.com/njh/W5100MacRaw
+category=Communication
+url=https://github.com/esp8266/Arduino
+architectures=rp2040
+dot_a_linkage=true
@@ -0,0 +1,8 @@
+#pragma once
+
+#include <LwipIntfDev.h>
+#include <utility/w6300.h>
+#include <LwipEthernet.h>
+#include <WiFi.h>
+
+using Wiznet6300lwIP = LwipIntfDev<Wiznet6300>;
@@ -0,0 +1,457 @@
+/*
+    Copyright (c) 2013, WIZnet Co., Ltd.
+    Copyright (c) 2016, Nicholas Humfrey
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions
+    are met:
+    1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+    ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+    FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+    COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+    SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+    HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+    STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+    OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+// original sources: https://github.com/njh/W5500MacRaw
+
+#include <SPI.h>
+#include "wiznet_pio_qspi.h"
+#include "w6300.h"
+#include <LwipEthernet.h>
+
+#define _W6300_SPI_READ_            (0x00 << 5)        ///< SPI interface Read operation in Control Phase
+#define _W6300_SPI_WRITE_           (0x01 << 5)        ///< SPI interface Write operation in Control Phase
+
+#define QSPI_SINGLE_MODE            (0x00 << 6) // 0b0000 0000 // 0x00
+#define QSPI_DUAL_MODE              (0x01 << 6) // 0b0100 0000 // 0x40
+#define QSPI_QUAD_MODE              (0x02 << 6) // 0b1000 0000 // 0x80 
+
+wiznet_pio_qspi_config_t wiznet_pio_qspi_config;
+wiznet_pio_qspi_handle_t wiznet_pio_qspi_handle = NULL;
+
+/**
+    Check physical link
+    @return true when physical link is up
+*/
+bool Wiznet6300::isLinked() {
+    ethernet_arch_lwip_gpio_mask();
+    ethernet_arch_lwip_begin();
+    auto ret = wizphy_getphylink() == PHY_LINK_ON;
+    ethernet_arch_lwip_end();
+    ethernet_arch_lwip_gpio_unmask();
+    return ret;
+}
+
+uint8_t Wiznet6300::wizchip_read(uint8_t block, uint16_t address) {
+    uint8_t ret = 0;
+    uint8_t opcode = 0;
+    uint16_t ADDR = 0;
+
+    wizchip_cs_select();
+
+    opcode = (uint8_t)((block & 0x000000FF) | (_W6300_SPI_READ_) | (QSPI_QUAD_MODE));
+    ADDR = (uint16_t)(address & 0x0000FFFF);
+    (*wiznet_pio_qspi_handle)->read_byte(opcode, ADDR, &ret, 1);
+
+    wizchip_cs_deselect();
+    return ret;
+}
+
+uint16_t Wiznet6300::wizchip_read_word(uint8_t block, uint16_t address) {
+    return ((uint16_t)wizchip_read(block, address) << 8) + wizchip_read(block, address + 1);
+}
+
+void Wiznet6300::wizchip_read_buf(uint8_t block, uint16_t address, uint8_t* pBuf, uint16_t len) {
+    uint8_t opcode = 0;
+    uint16_t ADDR = 0;
+
+    wizchip_cs_select();
+
+    opcode = (uint8_t)((block & 0x000000FF) | (_W6300_SPI_READ_) | (QSPI_QUAD_MODE));
+    ADDR = (uint16_t)(address & 0x0000FFFF);
+    (*wiznet_pio_qspi_handle)->read_byte(opcode, ADDR, pBuf, len);
+
+    wizchip_cs_deselect();
+}
+
+void Wiznet6300::wizchip_write(uint8_t block, uint16_t address, uint8_t wb) {
+    uint8_t opcode = 0;
+    uint16_t ADDR = 0;
+
+    wizchip_cs_select();
+
+    opcode = (uint8_t)((block & 0x000000FF) | (_W6300_SPI_WRITE_) | (QSPI_QUAD_MODE));
+    ADDR = (uint16_t)(address & 0x0000FFFF);
+    (*wiznet_pio_qspi_handle)->write_byte(opcode, ADDR, &wb, 1);
+
+    wizchip_cs_deselect();
+}
+
+void Wiznet6300::wizchip_write_word(uint8_t block, uint16_t address, uint16_t word) {
+    wizchip_write(block, address, (uint8_t)(word >> 8));
+    wizchip_write(block, address + 1, (uint8_t)word);
+}
+
+void Wiznet6300::wizchip_write_buf(uint8_t block, uint16_t address, const uint8_t* pBuf,
+                                   uint16_t len) {
+    uint8_t opcode = 0;
+    uint16_t ADDR = 0;
+
+    wizchip_cs_select();
+
+    opcode = (uint8_t)((block & 0x000000FF) | (_W6300_SPI_WRITE_) | (QSPI_QUAD_MODE));
+    ADDR = (uint16_t)(address & 0x0000FFFF);
+    (*wiznet_pio_qspi_handle)->write_byte(opcode, ADDR, (uint8_t *)pBuf, len);
+
+    wizchip_cs_deselect();
+}
+
+void Wiznet6300::setSn_CR(uint8_t cr) {
+    // Write the command to the Command Register
+    wizchip_write(BlockSelectSReg, Sn_CR, cr);
+
+    // Now wait for the command to complete
+    while (wizchip_read(BlockSelectSReg, Sn_CR))
+        ;
+}
+
+uint16_t Wiznet6300::getSn_TX_FSR() {
+    uint16_t val = 0, val1 = 0;
+    do {
+        val1 = wizchip_read_word(BlockSelectSReg, Sn_TX_FSR);
+        if (val1 != 0) {
+            val = wizchip_read_word(BlockSelectSReg, Sn_TX_FSR);
+        }
+    } while (val != val1);
+    return val;
+}
+
+uint16_t Wiznet6300::getSn_RX_RSR() {
+    uint16_t val = 0, val1 = 0;
+    do {
+        val1 = wizchip_read_word(BlockSelectSReg, Sn_RX_RSR);
+        if (val1 != 0) {
+            val = wizchip_read_word(BlockSelectSReg, Sn_RX_RSR);
+        }
+    } while (val != val1);
+    return val;
+}
+
+void Wiznet6300::wizchip_send_data(const uint8_t* wizdata, uint16_t len) {
+    uint16_t ptr = 0;
+
+    if (len == 0) {
+        return;
+    }
+    ptr = getSn_TX_WR();
+    wizchip_write_buf(BlockSelectTxBuf, ptr, wizdata, len);
+
+    ptr += len;
+
+    setSn_TX_WR(ptr);
+}
+
+void Wiznet6300::wizchip_recv_data(uint8_t* wizdata, uint16_t len) {
+    uint16_t ptr;
+
+    if (len == 0) {
+        return;
+    }
+    ptr = getSn_RX_RD();
+    wizchip_read_buf(BlockSelectRxBuf, ptr, wizdata, len);
+    ptr += len;
+
+    setSn_RX_RD(ptr);
+}
+
+void Wiznet6300::wizchip_recv_ignore(uint16_t len) {
+    uint16_t ptr;
+
+    ptr = getSn_RX_RD();
+    ptr += len;
+    setSn_RX_RD(ptr);
+}
+
+bool Wiznet6300::wizchip_sw_reset() {
+    setChipLOCK(CHPLCKR_UNLOCK);
+    uint16_t count = 0;
+    do {
+        // Wait Unlock Complete
+        if (++count > 20) {
+            // Check retry count
+            return false; // Over Limit retry count
+        }
+    } while ((getStatus() & SYSR_CHPL_LOCK) ^ SYSR_CHPL_ULOCK); // Exit Wait Unlock Complete
+
+    setCommand0(0x0); // Software Reset
+
+    do {
+        // Wait Lock Complete
+        if (++count > 20) {
+            // Check retry count
+            return false; // Over Limit retry count
+        }
+
+    } while ((getStatus() & SYSR_CHPL_LOCK) ^ SYSR_CHPL_LOCK); // Exit Wait Lock Complete
+
+    return true;
+}
+
+int8_t Wiznet6300::wizphy_getphylink() {
+    int8_t tmp;
+    if (getPHYCFGR() & PHYCFGR_LNK_ON) {
+        tmp = PHY_LINK_ON;
+    } else {
+        tmp = PHY_LINK_OFF;
+    }
+    return tmp;
+}
+
+int8_t Wiznet6300::wizphy_getphypmode() {
+    int8_t tmp = 0;
+    if (getPHYCFGR() & PHYCFGR_OPMDC_PDOWN) {
+        tmp = PHY_POWER_DOWN;
+    } else {
+        tmp = PHY_POWER_NORM;
+    }
+    return tmp;
+}
+
+void Wiznet6300::wizphy_reset() {
+    uint8_t tmp = getPHYCFGR();
+    tmp &= PHYCFGR_RST;
+    setPHYCFGR(tmp);
+    tmp = getPHYCFGR();
+    tmp |= ~PHYCFGR_RST;
+    setPHYCFGR(tmp);
+}
+
+int8_t Wiznet6300::wizphy_setphypmode(uint8_t pmode) {
+    uint8_t tmp = 0;
+    tmp         = getPHYCFGR();
+    if ((tmp & PHYCFGR_OPMD) == 0) {
+        return -1;
+    }
+    tmp &= ~PHYCFGR_OPMDC_ALLA;
+    if (pmode == PHY_POWER_DOWN) {
+        tmp |= PHYCFGR_OPMDC_PDOWN;
+    } else {
+        tmp |= PHYCFGR_OPMDC_ALLA;
+    }
+    setPHYCFGR(tmp);
+    wizphy_reset();
+    tmp = getPHYCFGR();
+    if (pmode == PHY_POWER_DOWN) {
+        if (tmp & PHYCFGR_OPMDC_PDOWN) {
+            return 0;
+        }
+    } else {
+        if (tmp & PHYCFGR_OPMDC_ALLA) {
+            return 0;
+        }
+    }
+    return -1;
+}
+
+Wiznet6300::Wiznet6300(int8_t cs, SPIClass& spi, int8_t intr) : _spi(spi), _cs(cs), _intr(intr) {
+}
+
+bool Wiznet6300::begin(const uint8_t* mac_address, netif *net) {
+    wiznet_pio_qspi_config.clock_div_major = 4;
+    wiznet_pio_qspi_config.clock_div_minor = 0;
+    wiznet_pio_qspi_config.data_io0_pin = WIZNET_PIO_QSPI_DATA_IO0_PIN;
+    wiznet_pio_qspi_config.data_io1_pin = WIZNET_PIO_QSPI_DATA_IO1_PIN;
+    wiznet_pio_qspi_config.data_io2_pin = WIZNET_PIO_QSPI_DATA_IO2_PIN;
+    wiznet_pio_qspi_config.data_io3_pin = WIZNET_PIO_QSPI_DATA_IO3_PIN;
+    wiznet_pio_qspi_config.clock_pin = WIZNET_PIO_QSPI_SCK_PIN;
+    wiznet_pio_qspi_config.cs_pin = WIZNET_PIO_QSPI_CS_PIN;
+
+    if (wiznet_pio_qspi_handle != NULL) {
+        wiznet_pio_qspi_close(wiznet_pio_qspi_handle);
+    }
+    wiznet_pio_qspi_handle = wiznet_pio_qspi_open(&wiznet_pio_qspi_config);
+    (*wiznet_pio_qspi_handle)->set_active(wiznet_pio_qspi_handle);
+
+    _netif = net;
+    memcpy(_mac_address, mac_address, 6);
+
+    pinMode(_cs, OUTPUT);
+    wizchip_cs_deselect();
+
+    wizchip_sw_reset();
+
+    // Unlock
+    setChipLOCK(CHPLCKR_UNLOCK);
+    setNetLOCK(NETLCKR_UNLOCK);
+    setPHYLOCK(PHYLCKR_UNLOCK);
+
+    // W6100 CIDR0
+    // Version 97(dec) 0x61(hex)
+    int ver = getVERSIONR();
+
+    Serial.print("version = 0x");
+    Serial.println(ver, HEX);
+
+    if (ver != 0x61) {
+        return false;
+    }
+
+    // Use the full 32Kb of RAM for Socket 0
+    setSn_RXBUF_SIZE(32);
+    setSn_TXBUF_SIZE(32);
+
+    // Set our local MAC address
+    setSHAR(_mac_address);
+
+    // Open Socket 0 in MACRaw mode
+    setSn_MR(Sn_MR_MACRAW);
+    setSn_CR(Sn_CR_OPEN);
+    if (getSn_SR() != SOCK_MACRAW) {
+        // Failed to put socket 0 into MACRaw mode
+        return false;
+    }
+
+    Serial.println("MAC RAW mode!");
+
+    if (_intr >= 0) {
+
+        setSn_IR(0xff); // Clear everything
+
+
+        // Configure socket 0 interrupts
+        setSn_IMR(Sn_IMR_RECV); // we're not interested in Sn_IMR_SENDOK atm
+
+        // Enable socket 0 interrupts
+        setSIMR(SIMR_S0_INT);
+
+        // Disable unused interrupts
+        setIMR(0);
+
+        // Enable interrupt pin
+        setCommand1(SYCR1_IEN);
+
+    }
+
+    // Success
+    return true;
+}
+
+void Wiznet6300::end() {
+    setSn_CR(Sn_CR_CLOSE);
+
+    // clear all interrupt of the socket
+    setSn_IR(0xFF);
+
+    // Wait for socket to change to closed
+    while (getSn_SR() != SOCK_CLOSED)
+        ;
+}
+
+/*
+    uint16_t Wiznet6100::readFrame(uint8_t* buffer, uint16_t bufsize) {
+    uint16_t data_len = readFrameSize();
+
+    if (data_len == 0) {
+        return 0;
+    }
+
+    if (data_len > bufsize) {
+        // Packet is bigger than buffer - drop the packet
+        discardFrame(data_len);
+        return 0;
+    }
+
+    return readFrameData(buffer, data_len);
+    }
+*/
+
+uint16_t Wiznet6300::readFrameSize() {
+    setSn_IR(Sn_IR_RECV);
+
+    uint16_t len = getSn_RX_RSR();
+
+    if (len == 0) {
+        return 0;
+    }
+
+    uint8_t  head[2];
+    uint16_t data_len = 0;
+
+    wizchip_recv_data(head, 2);
+    setSn_CR(Sn_CR_RECV);
+
+    data_len = head[0];
+    data_len = (data_len << 8) + head[1];
+    data_len -= 2;
+
+    // Clear interrupt flags
+    setICLR(Sn_IRCLR_RECV);
+    return data_len;
+}
+
+void Wiznet6300::discardFrame(uint16_t framesize) {
+    wizchip_recv_ignore(framesize);
+    setSn_CR(Sn_CR_RECV);
+}
+
+uint16_t Wiznet6300::readFrameData(uint8_t* buffer, uint16_t framesize) {
+    wizchip_recv_data(buffer, framesize);
+    setSn_CR(Sn_CR_RECV);
+
+    // let lwIP deal with mac address filtering
+    return framesize;
+}
+
+uint16_t Wiznet6300::sendFrame(const uint8_t* buf, uint16_t len) {
+    ethernet_arch_lwip_gpio_mask(); // So we don't fire an IRQ and interrupt the send w/a receive!
+
+    // Wait for space in the transmit buffer
+    while (1) {
+        uint16_t freesize = getSn_TX_FSR();
+        if (getSn_SR() == SOCK_CLOSED) {
+            ethernet_arch_lwip_gpio_unmask();
+            return -1;
+        }
+        if (len <= freesize) {
+            break;
+        }
+    };
+
+    wizchip_send_data(buf, len);
+    setSn_CR(Sn_CR_SEND);
+
+    while (1) {
+        uint8_t tmp = getSn_IR();
+        if (tmp & Sn_IR_SENDOK) {
+            setSn_IR(Sn_IR_SENDOK);
+            // Packet sent ok
+            break;
+        } else if (tmp & Sn_IR_TIMEOUT) {
+            setSn_IR(Sn_IR_TIMEOUT);
+            // There was a timeout
+            ethernet_arch_lwip_gpio_unmask();
+            return -1;
+        }
+    }
+
+    ethernet_arch_lwip_gpio_unmask();
+    return len;
+}
@@ -0,0 +1,898 @@
+/*
+    Copyright (c) 2013, WIZnet Co., Ltd.
+    Copyright (c) 2016, Nicholas Humfrey
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions
+    are met:
+    1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+    ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+    FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+    COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+    SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+    HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+    STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+    OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+// original sources: https://github.com/njh/W5500MacRaw
+
+#ifndef W6300_H
+#define W6300_H
+
+#include <stdint.h>
+#include <Arduino.h>
+#include <SPI.h>
+#include <LwipEthernet.h>
+#include "wiznet_pio_qspi.h"
+
+#define WIZNET_PIO_QSPI_DATA_IO0_PIN   18
+#define WIZNET_PIO_QSPI_DATA_IO1_PIN   19
+#define WIZNET_PIO_QSPI_DATA_IO2_PIN   20
+#define WIZNET_PIO_QSPI_DATA_IO3_PIN   21
+#define WIZNET_PIO_QSPI_SCK_PIN        17
+#define WIZNET_PIO_QSPI_CS_PIN         16
+
+class Wiznet6300 {
+public:
+    /**
+        Constructor that uses the default hardware SPI pins
+        @param cs the Arduino Chip Select / Slave Select pin (default 10)
+    */
+    Wiznet6300(int8_t cs = SS, SPIClass &spi = SPI, int8_t intr = -1);
+
+    /**
+        Initialise the Ethernet controller
+        Must be called before sending or receiving Ethernet frames
+
+        @param address the local MAC address for the Ethernet interface
+        @return Returns true if setting up the Ethernet interface was successful
+    */
+    bool begin(const uint8_t* address, netif *net);
+
+    /**
+        Shut down the Ethernet controlled
+    */
+    void end();
+
+    /**
+        Send an Ethernet frame
+        @param data a pointer to the data to send
+        @param datalen the length of the data in the packet
+        @return the number of bytes transmitted
+    */
+    uint16_t sendFrame(const uint8_t* data, uint16_t datalen);
+
+    /**
+        Read an Ethernet frame
+        @param buffer a pointer to a buffer to write the packet to
+        @param bufsize the available space in the buffer
+        @return the length of the received packet
+               or 0 if no packet was received
+    */
+    uint16_t readFrame(uint8_t* buffer, uint16_t bufsize);
+
+    bool isLinked();
+
+    /**
+        Report whether ::isLinked() API is implemented
+        @return true when ::isLinked() API is implemented
+    */
+    constexpr bool isLinkDetectable() const {
+        return true;
+    }
+
+    constexpr bool needsSPI() const {
+        return true;
+    }
+
+protected:
+    static constexpr bool interruptIsPossible() {
+        return true;
+    }
+
+    static constexpr PinStatus interruptMode() {
+        return LOW;
+    }
+
+    /**
+        Read an Ethernet frame size
+        @return the length of data do receive
+               or 0 if no frame was received
+    */
+    uint16_t readFrameSize();
+
+    /**
+        discard an Ethernet frame
+        @param framesize readFrameSize()'s result
+    */
+    void discardFrame(uint16_t framesize);
+
+    /**
+        Read an Ethernet frame data
+           readFrameSize() must be called first,
+           its result must be passed into framesize parameter
+        @param buffer a pointer to a buffer to write the frame to
+        @param framesize readFrameSize()'s result
+        @return the length of the received frame
+               or 0 if a problem occurred
+    */
+    uint16_t readFrameData(uint8_t* frame, uint16_t framesize);
+
+private:
+    //< SPI interface Read operation in Control Phase
+    static const uint8_t AccessModeRead = (0x00 << 2);
+
+    //< SPI interface Read operation in Control Phase
+    static const uint8_t AccessModeWrite = (0x01 << 2);
+
+    //< Common register block in Control Phase
+    static const uint8_t BlockSelectCReg = (0x00 << 3);
+
+    //< Socket 0 register block in Control Phase
+    static const uint8_t BlockSelectSReg = (0x01);
+
+    //< Socket 0 Tx buffer address block
+    static const uint8_t BlockSelectTxBuf = (0x02);
+
+    //< Socket 0 Rx buffer address block
+    static const uint8_t BlockSelectRxBuf = (0x03);
+
+    //< SPI Fixed Data Mode Length
+    static const uint8_t FixedDataMode1 = 1;
+    static const uint8_t FixedDataMode2 = 2;
+    static const uint8_t FixedDataMode4 = 3;
+
+    SPIClass& _spi;
+    int8_t    _cs;
+    int8_t    _intr;
+    uint8_t   _mac_address[6];
+
+    /**
+        Default function to select chip.
+        @note This function help not to access wrong address. If you do not describe this function
+        or register any functions, null function is called.
+    */
+    inline void wizchip_cs_select() {
+        //digitalWrite(WIZNET_PIO_QSPI_CS_PIN, LOW);
+        wiznet_pio_qspi_frame_start();
+    }
+
+    /**
+        Default function to deselect chip.
+        @note This function help not to access wrong address. If you do not describe this function
+        or register any functions, null function is called.
+    */
+    inline void wizchip_cs_deselect() {
+        //digitalWrite(WIZNET_PIO_QSPI_CS_PIN, HIGH);
+        wiznet_pio_qspi_frame_end();
+    }
+
+    /**
+        Default function to read in SPI interface.
+        @note This function help not to access wrong address. If you do not describe this function
+        or register any functions, null function is called.
+    */
+    inline uint8_t wizchip_spi_read_byte() {
+        //return _spi.transfer(0);
+        return 0;
+    }
+
+    /**
+        Default function to write in SPI interface.
+        @note This function help not to access wrong address. If you do not describe this function
+        or register any functions, null function is called.
+    */
+    inline void wizchip_spi_write_byte(uint8_t wb) {
+        //_spi.transfer(wb);
+    }
+
+    /**
+        Read a 1 byte value from a register.
+        @param address Register address
+        @return The value of register
+    */
+    uint8_t wizchip_read(uint8_t block, uint16_t address);
+
+    /**
+        Reads a 2 byte value from a register.
+        @param address Register address
+        @return The value of register
+    */
+    uint16_t wizchip_read_word(uint8_t block, uint16_t address);
+
+    /**
+        It reads sequence data from registers.
+        @param address Register address
+        @param pBuf Pointer buffer to read data
+        @param len Data length
+    */
+    void wizchip_read_buf(uint8_t block, uint16_t address, uint8_t* pBuf, uint16_t len);
+
+    /**
+        Write a 1 byte value to a register.
+        @param address Register address
+        @param wb Write data
+        @return void
+    */
+    void wizchip_write(uint8_t block, uint16_t address, uint8_t wb);
+
+    /**
+        Write a 2 byte value to a register.
+        @param address Register address
+        @param wb Write data
+        @return void
+    */
+    void wizchip_write_word(uint8_t block, uint16_t address, uint16_t word);
+
+    /**
+        It writes sequence data to registers.
+        @param address Register address
+        @param pBuf Pointer buffer to write data
+        @param len Data length
+    */
+    void wizchip_write_buf(uint8_t block, uint16_t address, const uint8_t* pBuf, uint16_t len);
+
+    /**
+        Get @ref Sn_TX_FSR register
+        @return uint16_t. Value of @ref Sn_TX_FSR.
+    */
+    uint16_t getSn_TX_FSR();
+
+    /**
+        Get @ref Sn_RX_RSR register
+        @return uint16_t. Value of @ref Sn_RX_RSR.
+    */
+    uint16_t getSn_RX_RSR();
+
+    /**
+        Reset WIZCHIP by softly.
+    */
+    bool wizchip_sw_reset();
+
+    /**
+        Get the link status of phy in WIZCHIP
+    */
+    int8_t wizphy_getphylink();
+
+    /**
+        Get the power mode of PHY in WIZCHIP
+    */
+    int8_t wizphy_getphypmode();
+
+    /**
+        Reset Phy
+    */
+    void wizphy_reset();
+
+    /**
+        set the power mode of phy inside WIZCHIP. Refer to @ref PHYCFGR in W5500, @ref PHYSTATUS in
+        W5200
+        @param pmode Setting value of power down mode.
+    */
+    int8_t wizphy_setphypmode(uint8_t pmode);
+
+    /**
+        It copies data to internal TX memory
+
+        @details This function reads the Tx write pointer register and after that,
+        it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to
+        internal TX memory and updates the Tx write pointer register. This function is being called
+        by send() and sendto() function also.
+
+        @param wizdata Pointer buffer to write data
+        @param len Data length
+        @sa wizchip_recv_data()
+    */
+    void wizchip_send_data(const uint8_t* wizdata, uint16_t len);
+
+    /**
+        It copies data to your buffer from internal RX memory
+
+        @details This function read the Rx read pointer register and after that,
+        it copies the received data from internal RX memory
+        to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes.
+        This function is being called by recv() also.
+
+        @param wizdata Pointer buffer to read data
+        @param len Data length
+        @sa wizchip_send_data()
+    */
+    void wizchip_recv_data(uint8_t* wizdata, uint16_t len);
+
+    /**
+        It discard the received data in RX memory.
+        @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX
+        memory.
+        @param len Data length
+    */
+    void wizchip_recv_ignore(uint16_t len);
+
+    /** Common registers */
+    enum {
+        MR       = 0x4000,  ///< Mode Register address (R/W)
+        SHAR     = 0x4120,  ///< Source MAC Register address (R/W)
+        INTLEVEL = 0x0013,  ///< Set Interrupt low level timer register address (R/W)
+        IR       = 0x2100,  ///< Interrupt Register (R/W)
+        _IMR_    = 0x2104,  ///< Interrupt mask register (R/W)
+        SIR      = 0x2101,  ///< Socket Interrupt Register (R/W)
+        _SIMR_   = 0x2114,  ///< Socket Interrupt Mask Register (R/W)
+        _RTR_    = 0x2101,  ///< Timeout register address (1 is 100us) (R/W)
+        _RCR_    = 0x4200,  ///< Retry count register (R/W)
+        UIPR     = 0x0000,  ///< Unreachable IP register address in UDP mode (R)
+        UPORTR   = 0x0000,  ///< Unreachable Port register address in UDP mode (R)
+        PHYCFGR  = 0x3000,  ///< PHY Status Register (R/W)
+        VERSIONR = 0x0000,  ///< Chip version register address (R)
+        NETLCKR  = 0x41F5,  ///< Network lock register
+        CHPLCKR  = 0x41F4,  ///< Chip lock register
+        PHYLCKR  = 0x41F6,  ///< PHY lock register
+        SYSR     = 0x2000,  ///< System status register
+        SYCR0    = 0x2004,  ///< System command register 0
+        SYCR1    = 0x2005,  ///< System command register 1
+    };
+
+    /** Socket registers */
+    enum {
+        Sn_MR         = 0x0000,  ///< Socket Mode register (R/W)
+        Sn_CR         = 0x0010,  ///< Socket command register (R/W)
+        Sn_IR         = 0x0020,  ///< Socket interrupt register (R)
+        Sn_ICLR       = 0x0028,  ///< Socket Interrupt clear register (W)
+        Sn_SR         = 0x0030,  ///< Socket status register (R)
+        Sn_PORT       = 0x0114,  ///< Source port register (R/W)
+        Sn_DHAR       = 0x0118,  ///< Peer MAC register address (R/W)
+        Sn_DIPR       = 0x0120,  ///< Peer IP register address (R/W)
+        Sn_DPORT      = 0x0140,  ///< Peer port register address (R/W)
+        Sn_MSSR       = 0x0110,  ///< Maximum Segment Size(Sn_MSSR0) register address (R/W)
+        Sn_TOS        = 0x0104,  ///< IP Type of Service(TOS) Register (R/W)
+        Sn_TTL        = 0x0108,  ///< IP Time to live(TTL) Register (R/W)
+        Sn_RXBUF_SIZE = 0x0220,  ///< Receive memory size register (R/W)
+        Sn_TXBUF_SIZE = 0x0200,  ///< Transmit memory size register (R/W)
+        Sn_TX_FSR     = 0x0204,  ///< Transmit free memory size register (R)
+        Sn_TX_RD      = 0x0208,  ///< Transmit memory read pointer register address (R)
+        Sn_TX_WR      = 0x020C,  ///< Transmit memory write pointer register address (R/W)
+        Sn_RX_RSR     = 0x0224,  ///< Received data size register (R)
+        Sn_RX_RD      = 0x0228,  ///< Read point of Receive memory (R/W)
+        Sn_RX_WR      = 0x022C,  ///< Write point of Receive memory (R)
+        Sn_IMR        = 0x0024,  ///< Socket interrupt mask register (R)
+        Sn_FRAG       = 0x002D,  ///< Fragment field value in IP header register (R/W)
+        Sn_KPALVTR    = 0x002F,  ///< Keep Alive Timer register (R/W)
+    };
+
+    /** Mode register values */
+    enum {
+        MR_RST   = 0x80,  ///< Reset
+        MR_WOL   = 0x20,  ///< Wake on LAN
+        MR_PB    = 0x10,  ///< Ping block
+        MR_PPPOE = 0x08,  ///< Enable PPPoE
+        MR_FARP  = 0x02,  ///< Enable UDP_FORCE_ARP CHECK
+    };
+
+    /* Interrupt Register values */
+    enum {
+        IR_CONFLICT = 0x80,  ///< Check IP conflict
+        IR_UNREACH  = 0x40,  ///< Get the destination unreachable message in UDP sending
+        IR_PPPoE    = 0x20,  ///< Get the PPPoE close message
+        IR_MP       = 0x10,  ///< Get the magic packet interrupt
+    };
+
+    /* Interrupt Mask Register values */
+    enum {
+        IM_IR7 = 0x80,  ///< IP Conflict Interrupt Mask
+        IM_IR6 = 0x40,  ///< Destination unreachable Interrupt Mask
+        IM_IR5 = 0x20,  ///< PPPoE Close Interrupt Mask
+        IM_IR4 = 0x10,  ///< Magic Packet Interrupt Mask
+    };
+
+    /** Socket Mode Register values @ref Sn_MR */
+    enum {
+        Sn_MR_CLOSE  = 0x00,  ///< Unused socket
+        Sn_MR_TCP    = 0x01,  ///< TCP
+        Sn_MR_UDP    = 0x02,  ///< UDP
+        Sn_MR_MACRAW = 0x07,  ///< MAC LAYER RAW SOCK
+        Sn_MR_UCASTB = 0x10,  ///< Unicast Block in UDP Multicasting
+        Sn_MR_ND     = 0x20,  ///< No Delayed Ack(TCP), Multicast flag
+        Sn_MR_BCASTB = 0x40,  ///< Broadcast block in UDP Multicasting
+        Sn_MR_MULTI  = 0x80,  ///< Support UDP Multicasting
+        Sn_MR_MIP6B  = 0x10,  ///< IPv6 packet Blocking in @ref Sn_MR_MACRAW mode
+        Sn_MR_MMB    = 0x20,  ///< Multicast Blocking in @ref Sn_MR_MACRAW mode
+        Sn_MR_MFEN   = 0x80,  ///< MAC filter enable in @ref Sn_MR_MACRAW mode
+    };
+
+    /** Socket Command Register values */
+    enum {
+        Sn_CR_OPEN      = 0x01,  ///< Initialise or open socket
+        Sn_CR_LISTEN    = 0x02,  ///< Wait connection request in TCP mode (Server mode)
+        Sn_CR_CONNECT   = 0x04,  ///< Send connection request in TCP mode (Client mode)
+        Sn_CR_DISCON    = 0x08,  ///< Send closing request in TCP mode
+        Sn_CR_CLOSE     = 0x10,  ///< Close socket
+        Sn_CR_SEND      = 0x20,  ///< Update TX buffer pointer and send data
+        Sn_CR_SEND_MAC  = 0x21,  ///< Send data with MAC address, so without ARP process
+        Sn_CR_SEND_KEEP = 0x22,  ///< Send keep alive message
+        Sn_CR_RECV      = 0x40,  ///< Update RX buffer pointer and receive data
+    };
+
+    /** Socket Interrupt register values */
+    enum {
+        Sn_IR_CON     = 0x01,  ///< CON Interrupt
+        Sn_IR_DISCON  = 0x02,  ///< DISCON Interrupt
+        Sn_IR_RECV    = 0x04,  ///< RECV Interrupt
+        Sn_IR_TIMEOUT = 0x08,  ///< TIMEOUT Interrupt
+        Sn_IR_SENDOK  = 0x10,  ///< SEND_OK Interrupt
+    };
+
+    /** Socket Status Register values */
+    enum {
+        SOCK_CLOSED      = 0x00,  ///< Closed
+        SOCK_INIT        = 0x13,  ///< Initiate state
+        SOCK_LISTEN      = 0x14,  ///< Listen state
+        SOCK_SYNSENT     = 0x15,  ///< Connection state
+        SOCK_SYNRECV     = 0x16,  ///< Connection state
+        SOCK_ESTABLISHED = 0x17,  ///< Success to connect
+        SOCK_FIN_WAIT    = 0x18,  ///< Closing state
+        SOCK_CLOSING     = 0x1A,  ///< Closing state
+        SOCK_TIME_WAIT   = 0x1B,  ///< Closing state
+        SOCK_CLOSE_WAIT  = 0x1C,  ///< Closing state
+        SOCK_LAST_ACK    = 0x1D,  ///< Closing state
+        SOCK_UDP         = 0x22,  ///< UDP socket
+        SOCK_MACRAW      = 0x42,  ///< MAC raw mode socket
+    };
+
+    /* PHYCFGR register value */
+    enum {
+        PHYCFGR_RST         = ~(1 << 7),  //< For PHY reset, must operate AND mask.
+        PHYCFGR_OPMD        = (1 << 6),   // Configure PHY with OPMDC value
+        PHYCFGR_OPMDC_ALLA  = (7 << 3),
+        PHYCFGR_OPMDC_PDOWN = (6 << 3),
+        PHYCFGR_OPMDC_NA    = (5 << 3),
+        PHYCFGR_OPMDC_100FA = (4 << 3),
+        PHYCFGR_OPMDC_100F  = (3 << 3),
+        PHYCFGR_OPMDC_100H  = (2 << 3),
+        PHYCFGR_OPMDC_10F   = (1 << 3),
+        PHYCFGR_OPMDC_10H   = (0 << 3),
+        PHYCFGR_DPX_FULL    = (1 << 2),
+        PHYCFGR_DPX_HALF    = (0 << 2),
+        PHYCFGR_SPD_100     = (1 << 1),
+        PHYCFGR_SPD_10      = (0 << 1),
+        PHYCFGR_LNK_ON      = (1 << 0),
+        PHYCFGR_LNK_OFF     = (0 << 0),
+    };
+
+    /* Lock register commands */
+    enum {
+        CHPLCKR_UNLOCK      = 0xCE,
+        NETLCKR_UNLOCK      = 0x3A,
+        PHYLCKR_UNLOCK      = 0x53,
+    };
+
+    /* SYS Lock register commands */
+    enum {
+        SYSR_CHPL_LOCK      = (1 << 7),
+        SYSR_CHPL_ULOCK     = (0 << 7),
+    };
+
+    /* SYS1 register commands */
+    enum {
+        SYCR1_IEN           = 0x80,
+    };
+
+    /* Socket Interrupt Mask register */
+    enum {
+        SIMR_S7_INT         = 0x80,
+        SIMR_S6_INT         = 0x40,
+        SIMR_S5_INT         = 0x20,
+        SIMR_S4_INT         = 0x10,
+        SIMR_S3_INT         = 0x08,
+        SIMR_S2_INT         = 0x04,
+        SIMR_S1_INT         = 0x02,
+        SIMR_S0_INT         = 0x01,
+    };
+
+    /* Sn_IR Clear register */
+    enum {
+        Sn_IRCLR_SENDOK     = 0x10,
+        Sn_IRCLR_TIMEOUT    = 0x08,
+        Sn_IRCLR_RECV       = 0x04,
+        Sn_IRCLR_DISCON     = 0x02,
+        Sn_IRCLR_CON        = 0x01,
+    };
+
+    /* Socket n Interrupt Mask register */
+    enum {
+        Sn_IMR_SENDOK       = 0x10,
+        Sn_IMR_TIMEOUT      = 0x08,
+        Sn_IMR_RECV         = 0x04,
+        Sn_IMR_DISCON       = 0x02,
+        Sn_IMR_CON          = 0x01,
+    };
+
+    enum {
+        PHY_SPEED_10    = 0,  ///< Link Speed 10
+        PHY_SPEED_100   = 1,  ///< Link Speed 100
+        PHY_DUPLEX_HALF = 0,  ///< Link Half-Duplex
+        PHY_DUPLEX_FULL = 1,  ///< Link Full-Duplex
+        PHY_LINK_OFF    = 0,  ///< Link Off
+        PHY_LINK_ON     = 1,  ///< Link On
+        PHY_POWER_NORM  = 0,  ///< PHY power normal mode
+        PHY_POWER_DOWN  = 1,  ///< PHY power down mode
+    };
+
+    /**
+        Set Mode Register
+        @param (uint8_t)mr The value to be set.
+        @sa getMR()
+    */
+    inline void setMR(uint8_t mode) {
+        wizchip_write(BlockSelectCReg, MR, mode);
+    }
+
+    /**
+        Get Mode Register
+        @return uint8_t. The value of Mode register.
+        @sa setMR()
+    */
+    inline uint8_t getMR() {
+        return wizchip_read(BlockSelectCReg, MR);
+    }
+
+    /**
+        Reads the W6300 system status register
+        @return uint8_t
+    */
+    inline uint8_t getStatus() {
+        return wizchip_read(BlockSelectCReg, SYSR);
+    }
+
+    /**
+        Writes a W6300 command
+    */
+    inline void setCommand0(uint8_t cmd) {
+        wizchip_write(BlockSelectCReg, SYCR0, cmd);
+    }
+
+    /**
+        Writes a W6300 command
+    */
+    inline void setCommand1(uint8_t cmd) {
+        wizchip_write(BlockSelectCReg, SYCR1, cmd);
+    }
+
+    /**
+        Set local MAC address
+        @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6
+        bytes.
+        @sa getSHAR()
+    */
+    inline void setSHAR(const uint8_t* macaddr) {
+        wizchip_write_buf(BlockSelectCReg, SHAR, macaddr, 6);
+    }
+
+    /**
+        Get local MAC address
+        @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6
+        bytes.
+        @sa setSHAR()
+    */
+    inline void getSHAR(uint8_t* macaddr) {
+        wizchip_read_buf(BlockSelectCReg, SHAR, macaddr, 6);
+    }
+
+    /**
+        Set @ref IR register
+        @param (uint8_t)ir Value to set @ref IR register.
+        @sa getIR()
+    */
+    inline void setIR(uint8_t ir) {
+        wizchip_write(BlockSelectCReg, IR, (ir & 0xF0));
+    }
+
+    /**
+        Get @ref IR register
+        @return uint8_t. Value of @ref IR register.
+        @sa setIR()
+    */
+    inline uint8_t getIR() {
+        return wizchip_read(BlockSelectCReg, IR) & 0xF0;
+    }
+
+    /**
+        Set @ref SIR register
+        @param (uint8_t)ir Value to set @ref SIR register.
+        @sa getSIR()
+    */
+    inline void setSIR(uint8_t ir) {
+        wizchip_write(BlockSelectCReg, SIR, ir);
+    }
+
+    /**
+        Get @ref SIR register
+        @return uint8_t. Value of @ref SIR register.
+        @sa setSIR()
+    */
+    inline uint8_t getSIR() {
+        return wizchip_read(BlockSelectCReg, SIR);
+    }
+
+    /**
+        Set @ref _IMR_ register
+        @param (uint8_t)imr Value to set @ref _IMR_ register.
+        @sa getIMR()
+    */
+    inline void setIMR(uint8_t imr) {
+        wizchip_write(BlockSelectCReg, _IMR_, imr);
+    }
+
+    /**
+        Get @ref _IMR_ register
+        @return uint8_t. Value of @ref _IMR_ register.
+        @sa setIMR()
+    */
+    inline uint8_t getIMR() {
+        return wizchip_read(BlockSelectCReg, _IMR_);
+    }
+
+    /**
+        Set @ref _SIMR_ register
+        @param (uint8_t)imr Value to set @ref _SIMR_ register.
+        @sa getIMR()
+    */
+    inline void setSIMR(uint8_t imr) {
+        wizchip_write(BlockSelectCReg, _SIMR_, imr);
+    }
+
+    /**
+        Set @ref _SIMR_ register
+        @param (uint8_t)imr Value to set @ref _SIMR_ register.
+        @sa getIMR()
+    */
+    inline void setICLR(uint8_t imr) {
+        wizchip_write(BlockSelectSReg, Sn_ICLR, imr);
+    }
+
+    /**
+        Get @ref _SIMR_ register
+        @return uint8_t. Value of @ref _SIMR_ register.
+        @sa setSIMR()
+    */
+    inline uint8_t getSIMR() {
+        return wizchip_read(BlockSelectCReg, _SIMR_);
+    }
+
+    /**
+        Set @ref PHYCFGR register
+        @param (uint8_t)phycfgr Value to set @ref PHYCFGR register.
+        @sa getPHYCFGR()
+    */
+    inline void setPHYCFGR(uint8_t phycfgr) {
+        wizchip_write(BlockSelectCReg, PHYCFGR, phycfgr);
+    }
+
+    /**
+        Get @ref PHYCFGR register
+        @return uint8_t. Value of @ref PHYCFGR register.
+        @sa setPHYCFGR()
+    */
+    inline uint8_t getPHYCFGR() {
+        return wizchip_read(BlockSelectCReg, PHYCFGR);
+    }
+
+    /**
+        Sets the chip lock to
+        @param state
+    */
+    inline void setChipLOCK(uint8_t state) {
+        wizchip_write(BlockSelectCReg, CHPLCKR, state);
+    }
+
+    /**
+        Sets the PHY lock to
+        @param state
+    */
+    inline void setPHYLOCK(uint8_t state) {
+        wizchip_write(BlockSelectCReg, PHYLCKR, state);
+    }
+    /**
+        Sets the network lock to
+        @param state
+    */
+    inline void setNetLOCK(uint8_t state) {
+        wizchip_write(BlockSelectCReg, NETLCKR, state);
+    }
+
+    /**
+        Get @ref VERSIONR register
+        @return uint8_t. Value of @ref VERSIONR register.
+    */
+    inline uint8_t getVERSIONR() {
+        return wizchip_read(BlockSelectCReg, VERSIONR);
+    }
+
+    /**
+        Set @ref Sn_MR register
+        @param (uint8_t)mr Value to set @ref Sn_MR
+        @sa getSn_MR()
+    */
+    inline void setSn_MR(uint8_t mr) {
+        wizchip_write(BlockSelectSReg, Sn_MR, mr);
+    }
+
+    /**
+        Get @ref Sn_MR register
+        @return uint8_t. Value of @ref Sn_MR.
+        @sa setSn_MR()
+    */
+    inline uint8_t getSn_MR() {
+        return wizchip_read(BlockSelectSReg, Sn_MR);
+    }
+
+    /**
+        Set @ref Sn_CR register, then wait for the command to execute
+        @param (uint8_t)cr Value to set @ref Sn_CR
+        @sa getSn_CR()
+    */
+    void setSn_CR(uint8_t cr);
+
+    /**
+        Get @ref Sn_CR register
+        @return uint8_t. Value of @ref Sn_CR.
+        @sa setSn_CR()
+    */
+    inline uint8_t getSn_CR() {
+        return wizchip_read(BlockSelectSReg, Sn_CR);
+    }
+
+    /**
+        Set @ref Sn_IR register
+        @param (uint8_t)ir Value to set @ref Sn_IR
+        @sa getSn_IR()
+    */
+    inline void setSn_IR(uint8_t ir) {
+        wizchip_write(BlockSelectSReg, Sn_IR, (ir & 0x1F));
+    }
+
+    /**
+        Get @ref Sn_IR register
+        @return uint8_t. Value of @ref Sn_IR.
+        @sa setSn_IR()
+    */
+    inline uint8_t getSn_IR() {
+        return (wizchip_read(BlockSelectSReg, Sn_IR) & 0x1F);
+    }
+
+    /**
+        Set @ref Sn_IMR register
+        @param (uint8_t)imr Value to set @ref Sn_IMR
+        @sa getSn_IMR()
+    */
+    inline void setSn_IMR(uint8_t imr) {
+        wizchip_write(BlockSelectSReg, Sn_IMR, (imr & 0x1F));
+    }
+
+    /**
+        Get @ref Sn_IMR register
+        @return uint8_t. Value of @ref Sn_IMR.
+        @sa setSn_IMR()
+    */
+    inline uint8_t getSn_IMR() {
+        return (wizchip_read(BlockSelectSReg, Sn_IMR) & 0x1F);
+    }
+
+    /**
+        Get @ref Sn_SR register
+        @return uint8_t. Value of @ref Sn_SR.
+    */
+    inline uint8_t getSn_SR() {
+        return wizchip_read(BlockSelectSReg, Sn_SR);
+    }
+
+    /**
+        Set @ref Sn_RXBUF_SIZE register
+        @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE
+        @sa getSn_RXBUF_SIZE()
+    */
+    inline void setSn_RXBUF_SIZE(uint8_t rxbufsize) {
+        // W6300 DEBUG: rxbufsize = 16
+        // W6300 DEBUG: original code:
+        /*   static inline uint8_t writeSn(SOCKET s=0, uint16_t addr, uint8_t data=16) {
+            return write(CH_BASE() + s * CH_SIZE + addr, data);
+        */
+        wizchip_write(BlockSelectSReg, Sn_RXBUF_SIZE, rxbufsize);
+    }
+
+    /**
+        Get @ref Sn_RXBUF_SIZE register
+        @return uint8_t. Value of @ref Sn_RXBUF_SIZE.
+        @sa setSn_RXBUF_SIZE()
+    */
+    inline uint8_t getSn_RXBUF_SIZE() {
+        return wizchip_read(BlockSelectSReg, Sn_RXBUF_SIZE);
+    }
+
+    /**
+        Set @ref Sn_TXBUF_SIZE register
+        @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE
+        @sa getSn_TXBUF_SIZE()
+    */
+    inline void setSn_TXBUF_SIZE(uint8_t txbufsize) {
+        wizchip_write(BlockSelectSReg, Sn_TXBUF_SIZE, txbufsize);
+    }
+
+    /**
+        Get @ref Sn_TXBUF_SIZE register
+        @return uint8_t. Value of @ref Sn_TXBUF_SIZE.
+        @sa setSn_TXBUF_SIZE()
+    */
+    inline uint8_t getSn_TXBUF_SIZE() {
+        return wizchip_read(BlockSelectSReg, Sn_TXBUF_SIZE);
+    }
+
+    /**
+        Get @ref Sn_TX_RD register
+        @return uint16_t. Value of @ref Sn_TX_RD.
+    */
+    inline uint16_t getSn_TX_RD() {
+        return wizchip_read_word(BlockSelectSReg, Sn_TX_RD);
+    }
+
+    /**
+        Set @ref Sn_TX_WR register
+        @param (uint16_t)txwr Value to set @ref Sn_TX_WR
+        @sa GetSn_TX_WR()
+    */
+    inline void setSn_TX_WR(uint16_t txwr) {
+        wizchip_write_word(BlockSelectSReg, Sn_TX_WR, txwr);
+    }
+
+    /**
+        Get @ref Sn_TX_WR register
+        @return uint16_t. Value of @ref Sn_TX_WR.
+        @sa setSn_TX_WR()
+    */
+    inline uint16_t getSn_TX_WR() {
+        return wizchip_read_word(BlockSelectSReg, Sn_TX_WR);
+    }
+
+    /**
+        Set @ref Sn_RX_RD register
+        @param (uint16_t)rxrd Value to set @ref Sn_RX_RD
+        @sa getSn_RX_RD()
+    */
+    inline void setSn_RX_RD(uint16_t rxrd) {
+        wizchip_write_word(BlockSelectSReg, Sn_RX_RD, rxrd);
+    }
+
+    /**
+        Get @ref Sn_RX_RD register
+        @return uint16_t. Value of @ref Sn_RX_RD.
+        @sa setSn_RX_RD()
+    */
+    inline uint16_t getSn_RX_RD() {
+        return wizchip_read_word(BlockSelectSReg, Sn_RX_RD);
+    }
+
+    /**
+        Get @ref Sn_RX_WR register
+        @return uint16_t. Value of @ref Sn_RX_WR.
+    */
+    inline uint16_t getSn_RX_WR() {
+        return wizchip_read_word(BlockSelectSReg, Sn_RX_WR);
+    }
+
+    netif *_netif;
+};
+
+#endif  // W6300_H
@@ -0,0 +1,400 @@
+/*
+    Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
+
+    SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "pico/stdlib.h"
+#include "pico/error.h"
+
+#include "hardware/dma.h"
+#include "hardware/clocks.h"
+
+#include "wiznet_pio_qspi.h"
+#include "wiznet_pio_qspi.pio.h"
+
+#ifndef PIO_QSPI_PREFERRED_PIO
+#define PIO_QSPI_PREFERRED_PIO 1
+#endif
+
+#define PADS_DRIVE_STRENGTH PADS_BANK0_GPIO0_DRIVE_VALUE_12MA
+#define IRQ_SAMPLE_DELAY_NS 100
+
+#define WIZNET_PIO_QSPI_PROGRAM_NAME wizchip_pio_spi_quad_write_read
+#define WIZNET_PIO_QSPI_PROGRAM_FUNC __CONCAT(WIZNET_PIO_QSPI_PROGRAM_NAME, _program)
+#define WIZNET_PIO_QSPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC __CONCAT(WIZNET_PIO_QSPI_PROGRAM_NAME, _program_get_default_config)
+#define WIZNET_PIO_QSPI_OFFSET_WRITE_BITS __CONCAT(WIZNET_PIO_QSPI_PROGRAM_NAME, _offset_write_bits)
+#define WIZNET_PIO_QSPI_OFFSET_WRITE_BITS_END __CONCAT(WIZNET_PIO_QSPI_PROGRAM_NAME, _offset_write_bits_end)
+#define WIZNET_PIO_QSPI_OFFSET_READ_END __CONCAT(WIZNET_PIO_QSPI_PROGRAM_NAME, _offset_read_bits_end)
+
+// All wiznet spi operations must start with writing a 3 byte header
+#define WIZNET_PIO_QSPI_HEADER_LEN 3
+
+#ifndef WIZNET_PICO_PIO_QSPI_INSTANCE_COUNT
+#define WIZNET_PICO_PIO_QSPI_INSTANCE_COUNT 1
+#endif
+
+typedef struct wiznet_pio_qspi_state {
+    wiznet_pio_qspi_funcs_t *funcs;
+    const wiznet_pio_qspi_config_t *qspi_config;
+    pio_hw_t *pio;
+    uint8_t pio_func_sel;
+    int8_t pio_offset;
+    int8_t pio_sm;
+    int8_t dma_out;
+    int8_t dma_in;
+    uint8_t qspi_header[WIZNET_PIO_QSPI_HEADER_LEN];
+    uint8_t qspi_header_count;
+} wiznet_pio_qspi_state_t;
+
+static wiznet_pio_qspi_state_t wiznet_pio_qspi_state[WIZNET_PICO_PIO_QSPI_INSTANCE_COUNT];
+static wiznet_pio_qspi_state_t *active_state;
+
+static wiznet_pio_qspi_funcs_t *get_wiznet_pio_qspi_impl(void);
+
+static uint16_t mk_cmd_buf(uint8_t *pdst, uint8_t opcode, uint16_t addr) {
+    pdst[0] = ((opcode >> 7 & 0x01) << 4) | ((opcode >> 6 & 0x01) << 0);
+    pdst[1] = ((opcode >> 5 & 0x01) << 4) | ((opcode >> 4 & 0x01) << 0);
+    pdst[2] = ((opcode >> 3 & 0x01) << 4) | ((opcode >> 2 & 0x01) << 0);
+    pdst[3] = ((opcode >> 1 & 0x01) << 4) | ((opcode >> 0 & 0x01) << 0);
+
+    pdst[4] = ((uint8_t)(addr >> 8) & 0xFF);
+    pdst[5] = ((uint8_t)(addr >> 0) & 0xFF);
+
+    pdst[6] = 0;
+
+    return 6 + 1;
+}
+
+// Initialise our gpios
+static void pio_qspi_gpio_setup(wiznet_pio_qspi_state_t *state) {
+    // Setup DO and DI
+    gpio_init(state->qspi_config->data_io0_pin);
+    gpio_init(state->qspi_config->data_io1_pin);
+    gpio_init(state->qspi_config->data_io2_pin);
+    gpio_init(state->qspi_config->data_io3_pin);
+    gpio_set_dir(state->qspi_config->data_io0_pin, GPIO_OUT);
+    gpio_set_dir(state->qspi_config->data_io1_pin, GPIO_OUT);
+    gpio_set_dir(state->qspi_config->data_io2_pin, GPIO_OUT);
+    gpio_set_dir(state->qspi_config->data_io3_pin, GPIO_OUT);
+    gpio_put(state->qspi_config->data_io0_pin, false);
+    gpio_put(state->qspi_config->data_io1_pin, false);
+    gpio_put(state->qspi_config->data_io2_pin, false);
+    gpio_put(state->qspi_config->data_io3_pin, false);
+
+    // Setup CS
+    gpio_init(state->qspi_config->cs_pin);
+    gpio_set_dir(state->qspi_config->cs_pin, GPIO_OUT);
+    gpio_put(state->qspi_config->cs_pin, true);
+
+    // Setup reset
+    gpio_init(state->qspi_config->irq_pin);
+    gpio_set_dir(state->qspi_config->irq_pin, GPIO_IN);
+    gpio_set_pulls(state->qspi_config->irq_pin, false, false);
+}
+
+wiznet_pio_qspi_handle_t wiznet_pio_qspi_open(const wiznet_pio_qspi_config_t *qspi_config) {
+
+    wiznet_pio_qspi_state_t *state;
+    for (unsigned int i = 0; i < count_of(wiznet_pio_qspi_state); i++) {
+        if (!wiznet_pio_qspi_state[i].funcs) {
+            state = &wiznet_pio_qspi_state[i];
+            break;
+        }
+    }
+    assert(state);
+    if (!state) {
+        return NULL;
+    }
+    state->qspi_config = qspi_config;
+    state->funcs = get_wiznet_pio_qspi_impl();
+
+    pio_qspi_gpio_setup(state);
+
+    pio_hw_t *pios[2] = {pio0, pio1};
+    uint pio_index = PIO_QSPI_PREFERRED_PIO;
+
+    if (!pio_can_add_program(pios[pio_index], &WIZNET_PIO_QSPI_PROGRAM_FUNC)) {
+        pio_index ^= 1;
+        if (!pio_can_add_program(pios[pio_index], &WIZNET_PIO_QSPI_PROGRAM_FUNC)) {
+            return NULL;
+        }
+    }
+
+    state->pio = pios[pio_index];
+    state->dma_in = -1;
+    state->dma_out = -1;
+
+    static_assert(GPIO_FUNC_PIO1 == GPIO_FUNC_PIO0 + 1, "");
+    state->pio_func_sel = GPIO_FUNC_PIO0 + pio_index;
+    state->pio_sm = (int8_t)pio_claim_unused_sm(state->pio, false);
+    if (state->pio_sm < 0) {
+        wiznet_pio_qspi_close(&state->funcs);
+        return NULL;
+    }
+
+    state->pio_offset = pio_add_program(state->pio, &WIZNET_PIO_QSPI_PROGRAM_FUNC);
+    printf("[QSPI CLOCK SPEED : %.2lf MHz]\r\n\r\n", 66.5 / (state->qspi_config->clock_div_major + ((double)state->qspi_config->clock_div_minor / 256)));
+    pio_sm_config sm_config = WIZNET_PIO_QSPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(state->pio_offset);
+
+    sm_config_set_clkdiv_int_frac(&sm_config, state->qspi_config->clock_div_major, state->qspi_config->clock_div_minor);
+    hw_write_masked(&pads_bank0_hw->io[state->qspi_config->clock_pin],
+                    (uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB,
+                    PADS_BANK0_GPIO0_DRIVE_BITS
+                   );
+    hw_write_masked(&pads_bank0_hw->io[state->qspi_config->clock_pin],
+                    (uint)1 << PADS_BANK0_GPIO0_SLEWFAST_LSB,
+                    PADS_BANK0_GPIO0_SLEWFAST_BITS
+                   );
+
+    printf("\r\n[QSPI QUAD MODE]\r\n");
+    sm_config_set_out_pins(&sm_config, state->qspi_config->data_io0_pin, 4);
+    sm_config_set_in_pins(&sm_config, state->qspi_config->data_io0_pin);
+    sm_config_set_set_pins(&sm_config, state->qspi_config->data_io0_pin, 4);
+    sm_config_set_sideset(&sm_config, 1, false, false);
+    sm_config_set_sideset_pins(&sm_config, state->qspi_config->clock_pin);
+
+    sm_config_set_in_shift(&sm_config, false, true, 8);
+    sm_config_set_out_shift(&sm_config, false, true, 8);
+
+    hw_set_bits(&state->pio->input_sync_bypass,
+                (1u << state->qspi_config->data_io0_pin) | (1u << state->qspi_config->data_io1_pin) | (1u << state->qspi_config->data_io2_pin) | (1u << state->qspi_config->data_io3_pin));
+    pio_sm_set_config(state->pio, state->pio_sm, &sm_config);
+    pio_sm_set_consecutive_pindirs(state->pio, state->pio_sm, state->qspi_config->clock_pin, 1, true);
+
+    gpio_set_function(state->qspi_config->data_io0_pin, state->pio_func_sel);
+    gpio_set_function(state->qspi_config->data_io1_pin, state->pio_func_sel);
+    gpio_set_function(state->qspi_config->data_io2_pin, state->pio_func_sel);
+    gpio_set_function(state->qspi_config->data_io3_pin, state->pio_func_sel);
+
+    // Set data pin to pull down and schmitt
+    gpio_set_pulls(state->qspi_config->data_io0_pin, false, true);
+    gpio_set_pulls(state->qspi_config->data_io1_pin, false, true);
+    gpio_set_pulls(state->qspi_config->data_io2_pin, false, true);
+    gpio_set_pulls(state->qspi_config->data_io3_pin, false, true);
+    gpio_set_input_hysteresis_enabled(state->qspi_config->data_io0_pin, true);
+    gpio_set_input_hysteresis_enabled(state->qspi_config->data_io1_pin, true);
+    gpio_set_input_hysteresis_enabled(state->qspi_config->data_io2_pin, true);
+    gpio_set_input_hysteresis_enabled(state->qspi_config->data_io3_pin, true);
+    /* @todo: Implement to use. */
+
+    pio_sm_exec(state->pio, state->pio_sm, pio_encode_set(pio_pins, 1));
+
+    state->dma_out = (int8_t)dma_claim_unused_channel(false); // todo: Should be able to use one dma channel?
+    state->dma_in = (int8_t)dma_claim_unused_channel(false);
+    if (state->dma_out < 0 || state->dma_in < 0) {
+        wiznet_pio_qspi_close(&state->funcs);
+        return NULL;
+    }
+
+    return &state->funcs;
+
+}
+
+void wiznet_pio_qspi_close(wiznet_pio_qspi_handle_t handle) {
+
+    wiznet_pio_qspi_state_t *state = (wiznet_pio_qspi_state_t *)handle;
+    if (state) {
+        if (state->pio_sm >= 0) {
+            if (state->pio_offset != -1) {
+                pio_remove_program(state->pio, &WIZNET_PIO_QSPI_PROGRAM_FUNC, state->pio_offset);
+            }
+
+            pio_sm_unclaim(state->pio, state->pio_sm);
+        }
+        if (state->dma_out >= 0) {
+            dma_channel_unclaim(state->dma_out);
+            state->dma_out = -1;
+        }
+        if (state->dma_in >= 0) {
+            dma_channel_unclaim(state->dma_in);
+            state->dma_in = -1;
+        }
+        state->funcs = NULL;
+    }
+}
+
+static void cs_set(wiznet_pio_qspi_state_t *state, bool value) {
+    gpio_put(state->qspi_config->cs_pin, value);
+}
+
+static __noinline void ns_delay(uint32_t ns) {
+    // cycles = ns * clk_sys_hz / 1,000,000,000
+    uint32_t cycles = ns * (clock_get_hz(clk_sys) >> 16u) / (1000000000u >> 16u);
+    busy_wait_at_least_cycles(cycles);
+}
+
+void wiznet_pio_qspi_frame_start(void) {
+    assert(active_state);
+
+    gpio_set_function(active_state->qspi_config->data_io0_pin, active_state->pio_func_sel);
+    gpio_set_function(active_state->qspi_config->data_io1_pin, active_state->pio_func_sel);
+    gpio_set_function(active_state->qspi_config->data_io2_pin, active_state->pio_func_sel);
+    gpio_set_function(active_state->qspi_config->data_io3_pin, active_state->pio_func_sel);
+
+    gpio_set_function(active_state->qspi_config->clock_pin, active_state->pio_func_sel);
+    gpio_pull_down(active_state->qspi_config->clock_pin);
+
+    // Pull CS low
+    cs_set(active_state, false);
+}
+
+void wiznet_pio_qspi_frame_end(void) {
+    assert(active_state);
+    // from this point a positive edge will cause an IRQ to be pending
+    cs_set(active_state, true);
+    // we need to wait a bit in case the irq line is incorrectly high
+#ifdef IRQ_SAMPLE_DELAY_NS
+    ns_delay(IRQ_SAMPLE_DELAY_NS);
+#endif
+}
+
+// To read a byte we must first have been asked to write a 3 byte spi header
+void wiznet_pio_qspi_read_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *rx, uint16_t rx_length) {
+    uint8_t command_buf[8] = {0,};
+    uint16_t command_len = mk_cmd_buf(command_buf, op_code, AddrSel);
+    uint32_t loop_cnt = 0;
+
+    pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
+    pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + WIZNET_PIO_QSPI_OFFSET_READ_END - 1);
+    //pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset + PIO_SPI_OFFSET_WRITE_BITS, active_state->pio_offset + PIO_SPI_OFFSET_READ_BITS_END - 1);
+    pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
+
+    loop_cnt = 2;
+    pio_sm_set_pindirs_with_mask(active_state->pio,
+                                 active_state->pio_sm,
+                                 (1u << active_state->qspi_config->data_io0_pin) | (1u << active_state->qspi_config->data_io1_pin) | (1u << active_state->qspi_config->data_io2_pin) | (1u << active_state->qspi_config->data_io3_pin),
+                                 (1u << active_state->qspi_config->data_io0_pin) | (1u << active_state->qspi_config->data_io1_pin) | (1u << active_state->qspi_config->data_io2_pin) | (1u << active_state->qspi_config->data_io3_pin));
+
+    /* @todo: Implement to use. */
+
+    pio_sm_restart(active_state->pio, active_state->pio_sm);
+    pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
+
+    pio_sm_put(active_state->pio, active_state->pio_sm, command_len * loop_cnt - 1);
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_x, 32));
+
+    pio_sm_put(active_state->pio, active_state->pio_sm, rx_length - 1);
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_y, 32));
+
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_jmp(active_state->pio_offset));
+
+    dma_channel_abort(active_state->dma_out);
+    dma_channel_abort(active_state->dma_in);
+
+    dma_channel_config out_config = dma_channel_get_default_config(active_state->dma_out);
+    channel_config_set_transfer_data_size(&out_config, DMA_SIZE_8);
+    channel_config_set_bswap(&out_config, true);
+    channel_config_set_dreq(&out_config, pio_get_dreq(active_state->pio, active_state->pio_sm, true));
+    dma_channel_configure(active_state->dma_out, &out_config, &active_state->pio->txf[active_state->pio_sm], command_buf, command_len, true);
+
+    dma_channel_config in_config = dma_channel_get_default_config(active_state->dma_in);
+    channel_config_set_transfer_data_size(&in_config, DMA_SIZE_8);
+    channel_config_set_bswap(&in_config, true);
+    channel_config_set_dreq(&in_config, pio_get_dreq(active_state->pio, active_state->pio_sm, false));
+    channel_config_set_write_increment(&in_config, true);
+    channel_config_set_read_increment(&in_config, false);
+    dma_channel_configure(active_state->dma_in, &in_config, rx, &active_state->pio->rxf[active_state->pio_sm], rx_length, true);
+
+#if 1
+    pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
+
+    __compiler_memory_barrier();
+
+    dma_channel_wait_for_finish_blocking(active_state->dma_out);
+    dma_channel_wait_for_finish_blocking(active_state->dma_in);
+
+    __compiler_memory_barrier();
+
+    pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
+
+#endif
+}
+
+void wiznet_pio_qspi_write_byte(uint8_t op_code, uint16_t AddrSel, uint8_t *tx, uint16_t tx_length) {
+    uint8_t command_buf[8] = {0,};
+    uint16_t command_len = mk_cmd_buf(command_buf, op_code, AddrSel);
+    uint32_t loop_cnt = 0;
+    tx_length = tx_length + command_len;
+
+    pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
+    pio_sm_set_wrap(active_state->pio, active_state->pio_sm, active_state->pio_offset, active_state->pio_offset + WIZNET_PIO_QSPI_OFFSET_WRITE_BITS_END - 1);
+    pio_sm_clear_fifos(active_state->pio, active_state->pio_sm);
+
+    loop_cnt = 2;
+    pio_sm_set_pindirs_with_mask(active_state->pio,
+                                 active_state->pio_sm,
+                                 (1u << active_state->qspi_config->data_io0_pin) | (1u << active_state->qspi_config->data_io1_pin) | (1u << active_state->qspi_config->data_io2_pin) | (1u << active_state->qspi_config->data_io3_pin),
+                                 (1u << active_state->qspi_config->data_io0_pin) | (1u << active_state->qspi_config->data_io1_pin) | (1u << active_state->qspi_config->data_io2_pin) | (1u << active_state->qspi_config->data_io3_pin));
+
+    pio_sm_restart(active_state->pio, active_state->pio_sm);
+    pio_sm_clkdiv_restart(active_state->pio, active_state->pio_sm);
+    pio_sm_put(active_state->pio, active_state->pio_sm, tx_length * loop_cnt - 1);
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_x, 32));
+    pio_sm_put(active_state->pio, active_state->pio_sm, 0);
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_out(pio_y, 32));
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_jmp(active_state->pio_offset));
+    dma_channel_abort(active_state->dma_out);
+
+
+    dma_channel_config out_config = dma_channel_get_default_config(active_state->dma_out);
+    channel_config_set_transfer_data_size(&out_config, DMA_SIZE_8);
+    channel_config_set_bswap(&out_config, true);
+    channel_config_set_dreq(&out_config, pio_get_dreq(active_state->pio, active_state->pio_sm, true));
+
+    pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
+
+    dma_channel_configure(active_state->dma_out, &out_config, &active_state->pio->txf[active_state->pio_sm], command_buf, command_len, true);
+    dma_channel_wait_for_finish_blocking(active_state->dma_out);
+    dma_channel_configure(active_state->dma_out, &out_config, &active_state->pio->txf[active_state->pio_sm], tx, tx_length - command_len, true);
+    dma_channel_wait_for_finish_blocking(active_state->dma_out);
+
+    const uint32_t fdebug_tx_stall = 1u << (PIO_FDEBUG_TXSTALL_LSB + active_state->pio_sm);
+    active_state->pio->fdebug = fdebug_tx_stall;
+    // pio_sm_set_enabled(active_state->pio, active_state->pio_sm, true);
+    while (!(active_state->pio->fdebug & fdebug_tx_stall)) {
+        tight_loop_contents(); // todo timeout
+    }
+    __compiler_memory_barrier();
+    pio_sm_set_consecutive_pindirs(active_state->pio, active_state->pio_sm, active_state->qspi_config->data_io0_pin, 4, false);
+
+    pio_sm_exec(active_state->pio, active_state->pio_sm, pio_encode_mov(pio_pins, pio_null));
+    pio_sm_set_enabled(active_state->pio, active_state->pio_sm, false);
+}
+
+static void wiznet_pio_qspi_set_active(wiznet_pio_qspi_handle_t handle) {
+    active_state = (wiznet_pio_qspi_state_t *)handle;
+}
+
+static void wiznet_pio_qspi_set_inactive(void) {
+    active_state = NULL;
+}
+
+static void wizchip_pio_qspi_reset(wiznet_pio_qspi_handle_t handle) {
+
+    wiznet_pio_qspi_state_t *state = (wiznet_pio_qspi_state_t *)handle;
+    gpio_set_dir(state->qspi_config->reset_pin, GPIO_OUT);
+    gpio_put(state->qspi_config->reset_pin, 0);
+    sleep_ms(100);
+    gpio_put(state->qspi_config->reset_pin, 1);
+    sleep_ms(100);
+
+}
+
+static wiznet_pio_qspi_funcs_t *get_wiznet_pio_qspi_impl(void) {
+    static wiznet_pio_qspi_funcs_t funcs = {
+        .close = wiznet_pio_qspi_close,
+        .set_active = wiznet_pio_qspi_set_active,
+        .set_inactive = wiznet_pio_qspi_set_inactive,
+        .frame_start = wiznet_pio_qspi_frame_start,
+        .frame_end = wiznet_pio_qspi_frame_end,
+        .read_byte = wiznet_pio_qspi_read_byte,
+        .write_byte = wiznet_pio_qspi_write_byte,
+        .reset = wizchip_pio_qspi_reset,
+    };
+    return &funcs;
+}
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Earle F. Philhower, III	6fc3165d3a	Update version	2025-06-19 18:36:46 -07:00
Maximilian Gerhardt	5dba6f2d1c	Fix JLink device names for RP2350 in PIO boards (#3001 )	2025-06-19 18:30:37 -07:00
Stefan Krüger	53583b2d8e	Add BigTreeTech SKR-Pico (#2988 )	2025-06-19 12:36:20 -07:00
Shubham Patel	327f10cc7e	Add Waveshare RP2350 Plus (#3000 ) * Add Waveshare RP2350 Plus * Refactor to use flash size menu Replaces separate board entries for Waveshare RP2350 Plus 4MB and 16MB variants with a flash size menu.	2025-06-19 11:55:06 -07:00
wiznet-mason	a7380a5de0	Add support for W6300-EVB-Pico and W6300-EVB-Pico2 boards (#2999 )	2025-06-19 11:16:53 -07:00
Earle F. Philhower, III	878271e122	Verify ADCInput buffer sizes legal for 3 and 4 inputs (#2996 ) Related to #2991, the ADCInput bufferWords needs to be a size that always has the 1st ADC sample at offset 0:0. For 1 and 2 inputs that's guaranteed. For 3 inputs we need a multiple of 3 words to ensure things always align in the case of overflow. For 4 inputs, a multiple of 2 words is needed.	2025-06-16 12:29:12 -07:00
Shubham Patel	1df647a104	Add Waveshare RP2350 LCD 0.96 (#2997 )	2025-06-16 12:18:01 -07:00
Earle F. Philhower, III	f07079bb7d	Remove dead debug code in PIOProgram (#2992 )	2025-06-12 11:15:12 -07:00
Earle F. Philhower, III	e7a23550ce	Update to GCC 14.3, Newlib 4.5.0 (#2975 ) Moves to just released GCC 14.3 Moves to full-fat printf/scanf because Newlib no longer supports all the calls libstdc++ requires with the older, smaller, nano-formatted-io option. Moves to latest SDK develop branch with important float acceleration fixes for the RP2350, among other updates. Moves to latest pioasm, picotool develop branches * SDK was refactored, update the includes * Rebuild PicoSDK and BearSSL libs * Update certs in BSSL validation example * Don't spell check the certs! * Updated tools with full fat++ newlib printf/scanf	2025-06-12 10:54:37 -07:00
Earle F. Philhower, III	0beb2d4ae8	Add SDIO PIN definitions for Adafruit Metro RP2040 (#2989 ) Fixes #2985	2025-06-12 08:16:55 -07:00
Maximilian Gerhardt	4de3ea94a9	Cleanly install PlatformIO platform from scratch (#2982 ) Prevents weird update errors stemming from an already installed platform (cached), then updating some files in it manually and then pio pkg updating it.	2025-06-01 08:08:45 -07:00
Maximilian Gerhardt	68f1da5f94	Mark all boards as picosdk compatible in PlatformIO board definition (#2980 )	2025-05-31 12:19:21 -07:00
Earle F. Philhower, III	948e9bfd22	Clear any existing IP before sending a DHCP request (#2979 ) Fixes #2978	2025-05-31 11:20:14 -07:00
Earle F. Philhower, III	73bd6a0891	Send DHCP request on ::begin even if lease exists (#2977 ) When a link comes up, we were only sending a DHCP request if the existing netif's ipaddress was 0. When a DHCP lease is acquired at first that IP is changed to the given address, and if we do another ::begin we wouldn't dhcp_start to send a new request and use the old one (until its lease expired). In the case of network changing (i.e. WiFiMulti on different nets or moving an Ethernet cable to another router) that old address would not be valid. Track if an IP address has been manually set and use that to determine if DHCP needs to be re-requested instead of looking at the old netif's ipaddress. Fixes #2974	2025-05-31 09:19:42 -07:00
Earle F. Philhower, III	f3df355663	Fix BSTstackLib service UUID reporting to client (#2968 ) Fixes #2967	2025-05-22 12:34:26 -07:00
Earle F. Philhower, III	7dcfe4d483	Update version	2025-05-22 08:19:51 -07:00
Lorandil	3df1392a1b	Added 'TwoWire::setBufferSize()' to Wire library (#2962 ) 'setBufferSize()' allows to modify the receive buffer size (inspired by the ESP32 code)	2025-05-21 13:57:35 -07:00
Earle F. Philhower, III	7c51742522	Add PSRAM option for Adafruit Metro RP2350 (#2961 ) Fixes #2960	2025-05-16 08:34:01 -07:00
Earle F. Philhower, III	08353deb88	Ignore libpico build dirs for git	2025-05-14 15:00:03 -07:00
Earle F. Philhower, III	d5e844b2bd	Panic on stack protector crash instead of exit (#2955 ) Newlib has a stack protector fail handler which write(2)s a message to STDERR which doesn't work here. Override with a call to panic(). Tell GCC to protect all functions for stack protection instead of ones that it heuristically decides need protection. Slower but safer, and only when stack protection is enabled.	2025-05-14 07:38:25 -07:00
Ricardo Marques	de7f1a7e83	Fixed generic PIN_LED and SPI0 Pin assignment on WIZnet W55RP20-EVB-Pico. (#2956 ) * Update pins_arduino.h Changed PIN_LED to match USERLED on PCB. Removed unavailable pins from SPI0 connection. * Update pins_arduino.h Uncommented SPI0 pins and reassigned them over GPIO 2,3,4,5.	2025-05-13 17:18:04 -07:00
jeroenzwanandjeroen	19b14898ea	Add target platform for compiling (#2939 ) * add target platform for compiling * added target specification for riscv --------- Co-authored-by: jeroen <jeroen.zwanepol@tective.nl>	2025-05-09 07:57:50 -07:00
Jan-Philipp	304e9ce2d1	Make Arduino IDE ask for OTA password (#2938 )	2025-05-07 09:03:29 -07:00
Earle F. Philhower, III	2bc00bef57	Fix ADCInput masking (#2937 ) Fixes #2935 The PICO_2350A patch flipped the logic of the ADCInput bitmask calcs causing the 2040 and 2350A to use bitmasks for the 2350B (i.e. wrong GPIOs) and vice versa.	2025-05-05 09:16:29 -07:00
Earle F. Philhower, III	47c2cd2b0b	Update version	2025-05-02 08:59:52 -07:00
Ahmed ARIFandAhmed ARIF	59614a99c8	optimize parity calculations in SerialPIO (#2932 ) (#2933 ) use bit manipulation technique from http://www.graphics.stanford.edu/~seander/bithacks.html#ParityParallel for parity calculation Co-authored-by: Ahmed ARIF <contact@eotics.com>	2025-05-01 14:06:52 -07:00
Earle F. Philhower, III	227d71ed18	Fix RP2350B SPI RX pin list (#2931 ) Fixes #2930	2025-04-29 16:29:45 -07:00
Earle F. Philhower, III	5e74bbbbb2	Rewrite SerialPIO receive path, ensure proper edge (#2929 ) The SerialPIO(SoftwareSerial) receive path was convoluted and required a lot of work on the host to get the actual data out. It also wasn't always sampling on the proper edge leading to errors whenever clocks or hold times shifted slightly. Rewrite the SerialPIO RX path to explicitily wait for start bit, pause 1/2 bit time, then idle for a full bit time for all bits. Takes more PIO instruction memory but works flawlessly even with mismatched clocks. Tested with a loopback from HW UART to SW UART with a 5% clock mismatch @ 19200 baud without reception errors, whereas the original code would fail with less than a 0.5% variation. Fixes #2928 ```` SoftwareSerial s(15, -1); void setup() { Serial1.setTX(0); Serial1.begin(19200 + 1920/2, SERIAL_8N1); s.begin(19200, SERIAL_8N1); } void loop() { Serial.println("---"); Serial1.write("Had we but world enough and time", 32); uint32_t now = millis(); while (millis() - now < 500) { while (s.available()) { auto c = s.read(); Serial.printf("%02x '%c'\n", c, c); } } } ````	2025-04-29 13:39:34 -07:00
Earle F. Philhower, III	8d58a9207f	Update LittleFS and Adafruit USB libraries (#2919 ) Only very minor changes to the submodules were noted. Should not have any effect on this core.	2025-04-18 18:00:56 -07:00
Earle F. Philhower, III	bc5b2c24ff	Fix rp2040.getCycleCount() from core1 (#2915 ) Fixes #2914 There are 2 systick units, one per core. Set up and start core1's systick unit and track each core's epoch separately. Document a method of preserving 100% user-only code on core1 and add a core1_disable_systick boolean flag that works like the separate stack one.	2025-04-18 09:16:36 -07:00
Wai WengandKong Wai Weng	40b9d5b07e	Add pin definitions for I2C1 on Cytron IRIV (#2916 ) Co-authored-by: Kong Wai Weng <waiweng@cytron.io>	2025-04-18 08:59:23 -07:00
Earle F. Philhower, III	07ea22d877	Generate PWMAudio pacer frequencies for 176/276MHz (#2913 ) Overclock settings changed, need to update the precalculated pacer fractions for PWMAudio.	2025-04-17 08:21:14 -07:00
Earle F. Philhower, III	253e946dcb	Update tools README.md	2025-04-17 07:04:26 -07:00
Earle F. Philhower, III	60d28d6c92	Add PIO.h header verification to CI (#2911 ) * Add PIO.h header verification to CI Ensure all PIO .pio.h headers match the .pio sources in the tree * Install all tools for Style check * Clean up mismatched PIO headers No functional changes, but the PDM pdm.pio file did not init a data pin while the pdm.pio.h (the one actually used in the core) did. Correct to match. * No need for submodules in the style check	2025-04-16 14:56:31 -07:00
Earle F. Philhower, III	e8bd9daa82	Update version	2025-04-16 13:22:14 -07:00
Earle F. Philhower, III	9747990c16	Fix remaining PICO_RP2350B reference (#2910 ) Minor fix to #2898	2025-04-16 08:28:53 -07:00
Liz ladyada Jeff Epler	6e48cffd62	add adafruit fruit jam and feather rp2350 adalogger (#2907 ) * add new RP2350 Metro! * lol * fruity! * Define HSTX pins on Adafruit boards with HSTX or DVI connectors * fixname * update rp2350b for fruit jam * add rp2350 adalogger (#9) adding rp2350 adalogger * update psram in makeboards * Update adafruit_fruitjam.json --------- Co-authored-by: ladyada <limor@ladyada.net> Co-authored-by: Jeff Epler <jepler@gmail.com>	2025-04-15 10:03:21 -07:00
Earle F. Philhower, III	9ac7892bd6	Update W55RP20 example for proper CS pin (#2906 ) Fixes #2903	2025-04-15 08:17:47 -07:00
Earle F. Philhower, III	073094fe0e	Update adc.rst for RP2350B	2025-04-15 07:39:17 -07:00
Earle F. Philhower, III	2a46bcfc0f	Update contrib.rst Update the PICO_RP2350A macro usage	2025-04-14 11:41:20 -07:00
Earle F. Philhower, III	e05dd50d62	Convert to SDK RP2350A/B determination (#2898 ) * Convert to SDK RP2350A/B determination Fixes #2878 The SDK uses `defined(PICO_RP2350) && !PICO_RP2350A` to indicate an RP2350B chip, not the define PICO_RP2350B. Match the SDK's usage by converting from `defined(PICO_RP2350B)` to `defined(PICO_RP2350) && !PICO_RP2350A` and update the chip variants accordingly. * Need to explicitly override PICO_RP2350A for all The SDK's board definition file hardcodes a PICO_RP2350A value for all boards, but we use the same board file for both A and B variants. Override the SDK board definition in the variant definition file. * Generic RP2350 needs 2-stage PICO_RP2350A setting Also ensure SDK board definition included before pins_arduino.h for clearing up redefinition errors. * Factor out undef PICO_RP2350A * Update Arduino.h	2025-04-08 16:02:54 -07:00
Earle F. Philhower, III	54885d79e0	Add explicit using arduino::IPAddress to headers (#2894 ) Fix issue with WiFiNINA includes. Fixes #2887	2025-04-07 10:17:03 -07:00
Earle F. Philhower, III	ecf2b2e39f	Add WiFi region for Pico2W (#2872 ) Fixes #2871	2025-03-19 08:47:12 -07:00
Earle F. Philhower, III	49397a7f3d	Update version	2025-03-18 17:03:18 -07:00
Earle F. Philhower, III	aabbba67ce	Add some Doxygen documentation to core and libraries (#2780 )	2025-03-18 17:00:44 -07:00
Earle F. Philhower, III	50b9ea99bd	Add Olimex Pico2XL and Pico2XXL (#2868 ) Fixes #2820	2025-03-18 16:40:51 -07:00
Earle F. Philhower, III	beece2ec9d	Add <1MB FS options for multi-size boards (#2867 ) Boards with selectable flash sizes only had a 1MB FS as the smallest option on 2MB boards. For the normal Pico @ 2MB, though, we supported filesystems down to 64KB. Add those same options to the 2MB SKUs of configurable boards.	2025-03-18 16:29:54 -07:00
Earle F. Philhower, III	1a8735700f	Use flash size menu for Olimex boards (#2866 ) Remove duplicated boards with just different flash sizes. Use the flash size menu to select 2 or 16 MB units.	2025-03-18 15:26:34 -07:00
Earle F. Philhower, III	cc1af990b4	Add Pimoroni Servo2040 (#2865 ) Fixes #2730 . Untested, based off of schematics	2025-03-18 15:11:25 -07:00
Eris Fairbanks	0ec1dc6724	Bidirectional TDM Support (#2843 ) * Initial commit. * Works with AK4619 in TDM128 I2S compatibility mode set to rising BCLK. * Works with I2S compat mode with BCLK mode set to 0 on AK4619.	2025-03-14 11:35:37 -07:00
Earle F. Philhower, III	15d1c6813a	Redo UF2 discovery for Windows compatibility (#2853 ) Windows Python doesn't seem to kill the worker Thread properly when the IDE is exited, leading to a) multiple Python3 instances on a PC after many uses and b) errors updating the core when it tries to re-install Python3 while still having the older version's EXE loaded and in use. When an exception happens on the input() call under Windows, it seems like it can still leave a thread running. Add one more flag, caught in a global exception handler. Works around https://github.com/arduino/arduino-cli/issues/2867	2025-03-14 10:08:37 -07:00
Earle F. Philhower, III	cdf0a65d0f	Fix invalid overclock speeds 175 and 275 MHz (#2855 ) Fixes #2854 Change 175->176 and 275->276 in CPU speed menu to avoid panic when attempting to set a clock that wasn't exactly possible.	2025-03-13 20:18:50 -07:00
Earle F. Philhower, III	e60858c327	Update version	2025-03-11 13:35:52 -07:00
Earle F. Philhower, III	bebd1dff50	Update README.md (#2848 )	2025-03-11 13:34:08 -07:00
Earle F. Philhower, III	14145e4469	Update to SDK 2.1.2-develop (#2844 ) Supercedes #2815 Move to pico-sdk official develop branch which includes a necessary IRQ header fix. 200MHz is now default for the Pico, but 133 is still available from the menus.	2025-03-11 13:30:17 -07:00
Dryw Wade	d9d556bcd0	Add SparkFun XRP Controller (#2847 )	2025-03-11 13:00:55 -07:00
InfiniteCoder	5bd1a3a0f6	A2DP: scanAsyncDone & scanAsyncResults; fix write and availableForWrite (#2839 )	2025-03-06 10:55:56 -08:00
Earle F. Philhower, III	5bfc35caf5	Enable add'l UART_AUX pinouts for RP2350 (#2837 ) Fixes #2835. Thanks @deltaford!	2025-03-05 07:02:32 -08:00
Alex Brudner	8e1e709ab1	Add SparkFun IoT RedBoard RP2350 (#2836 )	2025-03-03 16:30:42 -08:00
Jeff Epler	46a58fb4b5	Early out of (un)maskInterrupts() if no GPIO interrupts need to be masked (#2831 ) My application is designed to generate HSTX data on core0 in interrupts, but also uses hardware SPI for SD card access. It turns out that the amount of time spent in maskInterrupts/ unmaskInterrupts, even with an empty _usingIRQs, is too long. Add a quick check and avoid touching the interrupt disable flag if there's not actually any GPIO interrupt to (un)mask.	2025-02-28 12:44:47 -08:00
Earle F. Philhower, III	8deb6b9724	Adjust the PSRAM clock when over/underclock F_SYS (#2824 ) * Adjust the PSRAM clock when over/underclock F_SYS Fixes #2818 * Need to increase PSRAM divider before sysclk increase Per datasheet, when increasing sysclk speed we need to set the qmi clocks first and do a dummy transfer to ensure no invalid speed operations happen on the bus. Handle the logic for this while setting up the overclock.	2025-02-26 16:38:52 -08:00
Jeff Epler	6236d1f7c5	Define HSTX pins on Adafruit boards with HSTX or DVI connectors (#2825 )	2025-02-25 08:36:58 -08:00
Dryw Wade	91ce323a68	Add SparkFun XRP Controller (Beta) (#2823 )	2025-02-24 12:03:55 -08:00
Earle F. Philhower, III	2f82bfd22a	Update README.md	2025-02-23 11:36:36 -08:00
Michael Ring	1689c75ef1	Support Makerbase MKSTHR36 and MKSTHR42 Boards (#2819 ) * Support Makerbase MKSTHR36 and MKSTHR42 Boards * Added missing define for PIN_SERIAL1_* for MKSTHR42 Board	2025-02-23 11:35:53 -08:00
brabl2	935eb64a8e	Added WizNet W6100 to the AdvancedWebServer example (#2812 )	2025-02-19 07:25:09 -08:00