Earle F. Philhower, III
c64a4a58d7
Fix initial SPI startup ( #1970 )
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Clocks were not being set at all after #1934 . Ensure they are by initting
to an impossible 0hz clock on creation and ::end
Fixes #1969
2024-01-28 16:21:48 -08:00
Nerradia
02c272b091
Skip SPI re-init if clock frequency doesn't change ( #1934 )
2024-01-28 10:27:12 -08:00
Earle F. Philhower, III
c3a3526aad
Fix SPI 16-bit transfers ( #1882 )
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Fixes #1879
Fixes #1874
2023-12-04 17:30:43 -08:00
Earle F. Philhower, III
280fc43731
Fix SPI debug print warning ( #1881 )
2023-12-04 12:48:49 -08:00
Earle F. Philhower, III
6a878cdee8
Only create SPI/Wire instances if variant defined ( #1842 )
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Fixes #1841
2023-11-24 09:56:13 -08:00
Earle F. Philhower, III
5678bb9904
Don't break transfer16 into 2 8-bit CS periods ( #1764 )
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With HW chip select enabled, transfer16's 2 individual byte transfers will
actualy deassert CS for a brief instant between bytes. Avoid this by doing
a single multi-byte (2) tranfer of 16b.
2023-10-11 08:40:17 -07:00
Earle F. Philhower, III
52d50da56f
Avoid calling spi_set_format during SPI transfers ( #1762 )
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Avoid potential interaction with Pico SDK 1.5.1 update that causes hiccups in
SPI transmissions. SPI.transfer16 to use 8-bit transfers.
Fixes #1760
2023-10-11 08:22:01 -07:00
Earle F. Philhower, III
f60b7831c8
Add SPISlave class ( #1717 )
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Allows the Pico to behave as an SPI slave and allows apps to respond
with appropriate data through callbacks.
Fixes #1680
2023-09-17 15:23:03 -07:00
Earle F. Philhower, III
c48cdeeea0
Protect SPI transaction start/end from race conditions ( #1715 )
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It would be possible for an IRQ-driven SPI user to fire
while the main app's SPI.beginTransaction was in process.
This would result in incorrect state for the main app since
the IRQ may overwrite some settings that the app already
set.
Disable all IRQs around the begin and end processes to avoid
the possibility.
2023-09-16 13:59:37 -07:00
Earle F. Philhower, III
0be7c98dff
Support IRQ disabled SPI transactions ( #1714 )
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Fixes #1147
When SPI.beginTransaction() is called, disable all GPIO IRQs that were
registered using SPI.usingInterrupt(). On SPI.endTransaction(), restore
all the IRQs to their prior state.
2023-09-16 13:31:14 -07:00
Earle F. Philhower, III
456b474a48
Allow re-setting identical pins without panic() ( #1655 )
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Setting a pin to the current value is a no-op, not fatal.
Fixes #1652
2023-08-21 08:52:49 -07:00
LinusHeu
ca4637d14d
SPI debugging: tiny fix & log actual baudrate ( #1641 )
2023-08-10 07:39:36 -07:00
Carter Nelson
ba413bb7ad
Remove extra SPI byte flip ( #1202 )
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Fixes #1201
2023-02-17 12:42:31 -08:00
Vishnu Mohanan
8a1e03739a
Fix SPI transfer16 return value ( #1148 )
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The SPI transfer16() function returned wrongly oriented bytes. Replaced reverseByte() with reverse16Bit().
Fixes #1146
2023-01-31 08:09:53 -08:00
Earle F. Philhower, III
444bb24464
Remove debug printout warnings ( #1091 )
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Exposed by #1090 , remove ugly printf format warnings while in debug mode
2023-01-02 10:51:04 -08:00
Earle F. Philhower, III
e2b04e7405
Minor tweak, NULL=>nullptr ( #844 )
2022-09-07 14:41:04 -07:00
Earle F. Philhower, III
4d2f64a12b
Add bidirectional bulk SPI transfer, update SdFAT ( #819 )
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Should speed up SD transfers significantly (2.5x+).
See #801
2022-08-31 07:42:34 -07:00
Earle F. Philhower, III
10b869ef30
Fix XIAO RP2040, allow swapping HW units 0/1 ( #606 )
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Add plumbing to allow `Wire`, `Serial1`, `SPI1` to map to the 2nd
hardware unit for devices where the PCB layout only brings out the
2nd port.
Fix the Seeedstudio XAIO pins
Fixes #594
2022-06-04 21:37:28 -07:00
